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  <title>URCS Seminars &amp; Talks</title>
  <link>http://www.cs.rochester.edu/dept/seminar</link>
  <description>Upcoming Seminars &amp; Talks from the Computer Science Department at the University of Rochester</description>
  <language>en-us</language>
  <image>
   <url>http://www.cs.rochester.edu/images/monalogo.jpg</url>
   <title>Computer Science Department, University of Rochester</title>
   <link>http://www.cs.rochester.edu/dept/seminar</link>
  </image>
  <lastBuildDate>Sun, 02 Nov 2008 17:40:48 -0500</lastBuildDate>
  
   <item>
    <title>Alok Garg: Practice talk for MICRO 2008</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/373</link>
    <description>[Friday, November 07, 2008 at  2:00 PM in 703] http://www.ece.rochester.edu/~garg/document/garg.micro08.pdf

Optimizing the common case has been an adage in
decades of processor design practices. However, as
the system complexity and optimization techniques’
sophistication have increased sub- stantially,
maintaining correctness under all situations,
however unlikely, is contributing to the necessity
of extra conservatism in all layers of the system
design. The mounting process, voltage, and
temperature variation concerns further add to the
conservatism in setting operating
parameters. Excessive conservatism in turn hurt
performance and efficiency in the common
case. However, much of the system’s complexity
comes from advanced performance features and may
not compromise the whole system’s functionality
and correctness even if some components are
imperfect and introduce occasional errors. We
propose to separate performance goals from the
correctness goal using an explicitly-decoupled
architecture.  In this paper, we discuss one such
incarnation where an inde- pendent core serves as
an optimistic performance enhancement engine that
helps accelerate these correctness-guaranteeing
core by passing high-quality predictions and
performing accurate prefetching. The lack of
concern for correctness in the optimistic core
allows us to optimize its execution in a more
effective fashion than possible in optimizing a
monolithic core with correctness requirements. We
show that such a decoupled design allows
significant optimization benefits and is much less
sensitive to conservatism applied in the
correctness domain.</description>
    <pubDate>Sun, 02 Nov 2008 17:40:48 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/373</guid>
   </item>
  
   <item>
    <title>Hemayet Hossain: Practice talk for PACT 2008</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/363</link>
    <description>[Friday, October 17, 2008 at  2:00 AM in 703] Improving Support for Locality and Fine-Grain Sharing in Chip Multiprocessors

http://www.cs.rochester.edu/u/sandhya/papers/pact08.pdf</description>
    <pubDate>Mon, 13 Oct 2008 11:53:58 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/363</guid>
   </item>
  
   <item>
    <title>James Park: Summer Internship: ZFS @ ARNL</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/356</link>
    <description>[Friday, September 26, 2008 at  2:00 PM in 703] </description>
    <pubDate>Tue, 23 Sep 2008 16:39:27 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/356</guid>
   </item>
  
   <item>
    <title>Dr. Paul McKenney,: RCU in the Linux Kernel</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/350</link>
    <description>[Friday, October 24, 2008 at  2:00 PM in 703] Biography:
Paul E. McKenney is a Distinguished Engineer at the Linux Technology Center at IBM Beaverton. He obtained his Ph.D. in Computer Science and Engineering from the Oregon Health and Sciences Univerity. His research interests are in the intersection of SMP performance and scalability and realtime response. He has authored more than 20 research papers in SMP algorithms, communications congestion control algorithms, realtime response, and synchronization primitives. He is a member of the IBM Academy of Technology, and has been invited to the Linux Kernel Summit three times (2003-2005). He is a co-inventor of RCU, but given that something resembling RCU has been invented independently at least five times, this might not count for all that much. He holds 19 patents. </description>
    <pubDate>Mon, 08 Sep 2008 02:09:25 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/350</guid>
   </item>
  
   <item>
    <title>Michael F. Spear: Practice job talk</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/349</link>
    <description>[Friday, October 03, 2008 at  2:00 PM in 703] </description>
    <pubDate>Mon, 08 Sep 2008 02:07:08 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/349</guid>
   </item>
  
   <item>
    <title>RongRong Zhong: PVFS @ Argonne National Labs</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/348</link>
    <description>[Friday, September 19, 2008 at  2:00 PM in 703] </description>
    <pubDate>Mon, 08 Sep 2008 02:06:23 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/348</guid>
   </item>
  
   <item>
    <title>Christopher Stewart: Practice job talk</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/347</link>
    <description>[Friday, September 12, 2008 at  2:00 PM in 703] </description>
    <pubDate>Mon, 08 Sep 2008 02:05:05 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/347</guid>
   </item>
  
   <item>
    <title>Paul Francis: Scaling Internet Routing with Legacy Protocols</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/325</link>
    <description>[Friday, March 21, 2008 at  2:00 PM in 703] The large and constantly growing Internet routing table size is a                                                                                                         longstanding problem that leads to increased convergence time, increased boot                                                                                               time, and costly equipment upgrades.  The problem exists for both VPN and                                                                                                 
global routing tables, and there is concern that IPv4 address space                                                                                                       exhaustion over the next few years may lead to an increasingly fragmented                                                                                                  address space, poor aggregation, and therefore a increase in the rate of                                                                                                  routing table size.  To address these issues, the IETF is working hard on new                                                                                             protocols that will shrink routing tables.  In this talk, we present a way to                                                                                              shrink routing tables, easily by an order of magnitude or more, without any                                                                                               new protocols.  The idea behind our approach, called Virtual Aggregation, is                                                                                               to partition the address space into large Virtual Prefixes, each of which is                                                                                              delegated to a tunneled virtual network composed of a fraction of ISP                                                                                                     routers.  Virtual Aggregation can be used independently by a single ISP, or                                                                                               cooperatively among a group of ISPs.  This talk describes how Virtual                                                                                                     
Aggregation can be configured and deployed, and gives performance results                                                                                                 based on measurements made at a Tier-I ISP. &lt;br&gt;&lt;br&gt;
&lt;a href=http://www.cs.cornell.edu/people/francis/&quot;&gt; http://www.cs.cornell.edu/people/francis/ &lt;/a&gt;</description>
    <pubDate>Thu, 20 Mar 2008 13:33:25 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/325</guid>
   </item>
  
   <item>
    <title>Virendra Marathe: Improving the Performance of Nonblocking Software Transactional Memory</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/323</link>
    <description>[Friday, March 14, 2008 at  2:00 PM in 703] Transactional Memory (TM) is a promising concurrency control technology that is likely to replace traditionally used mutual exclusion locks in the upcoming multicore     
era.  TM research grew out of research in nonblocking concurrent algorithms.  Hence early software TM (STM) systems were all nonblocking.  However they incurred high     
overheads, rendering them largely impractical.                                                                                                                            
                                                                                                                                                                          
More recently, there has been a shift toward blocking implementations of STMs.  This has been accompanied by several significant performance optimizations, making        
blocking STMs far more practical.  A general hypothesis has emerged that nonblocking STMs are fundamentally slower than blocking STMs.  In this talk I will show that     
this hypothesis is false, and that nonblocking STMs can approach the performance of, and even outperform, state-of-the-art blocking STMs.  I will present several         
variants of our most recent nonblocking STM that is competitive with state-of-the-art blocking STMs.                               </description>
    <pubDate>Thu, 13 Mar 2008 18:30:09 -0400</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/323</guid>
   </item>
  
   <item>
    <title>Kai Shen: Replication Degree Customization for High Availability</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/317</link>
    <description>[Friday, March 28, 2008 at  2:00 PM in 703] Practice talk for Eurosys 2008. http://www.dcs.gla.ac.uk/Conferences/EuroSys2008/
&lt;br&gt;&lt;br&gt;


Object replication is a common approach to enhance the
availability of distributed data-intensive services and stor
age systems. Many such systems are known to have highly
skewed object request probability distributions. In this pa-
per, we propose an object replication degree customization
scheme that maximizes the expected service availability under given object request probabilities, object sizes, and space constraints (e.g., memory/storage capacities). In particular, we discover that the optimal replication degree of an object should be linear in the logarithm of its popularity-to-size ratio. We also study the feasibility and effectiveness of our proposed scheme using applications driven by real-life system object request traces and machine failure traces. When the data object popularity distribution is known a priori, our proposed customization can achieve 1.32­2.92 &quot;nines&quot; increase in system availability (or 21­74% space savings at the same availability level) compared to uniform replication. Results also suggest that our scheme requires a moderate amount of replica creation/removal overhead (weekly changes involve no more than 0.24% objects and no more than 0.11% of total data size) under realistic object request popularity changes.
&lt;br&gt;
&lt;a href=&quot;http://www.cs.rochester.edu/u/kshen/papers/eurosys2008.pdf&quot;&gt; &lt;FONT COLOR = &quot;BLUE&quot;&gt; [pdf] &lt;/FONT&gt; &lt;/a&gt;</description>
    <pubDate>Thu, 14 Feb 2008 15:16:51 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/317</guid>
   </item>
  
   <item>
    <title>Konstantinos Menychtas: Analysis of Tradeoffs in STM implementation</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/312</link>
    <description>[Friday, February 08, 2008 at  2:00 PM in 703] In this talk Kostas will describe his CS400 project.</description>
    <pubDate>Thu, 07 Feb 2008 15:55:34 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/312</guid>
   </item>
  
   <item>
    <title>Konstantinos Menychtas and James Park: 1st year Graduate Students</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/300</link>
    <description>[Friday, February 01, 2008 at  2:00 PM in 703] Stan (aka. James) will present his CS 400 project from last semester. </description>
    <pubDate>Thu, 07 Feb 2008 15:52:24 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/300</guid>
   </item>
  
   <item>
    <title>Virendra Marathe: Toward High Performance Nonblocking Software Transactional Memory</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/311</link>
    <description>[Friday, February 15, 2008 at  2:00 PM in 703] Practice talk for PPOPP 2008.
http://research.ihost.com/ppopp08/

Substantial advances in STM performance in recent years have
mostly focused on blocking systems. We describe our work integrating the most important techniques and optimizations emerging from the recent work on blocking STMs into several variants of a nonblocking STM.

In particular, our design is based on the philosophy of keep
ing the common, contention free execution path as simple (consequently fast) as possible, while resorting to the more expensive data displacement and metadata management only in situations where transactions have problems making forward progress. We employ novel ownership &quot;stealing&quot; and metadata management techniques in our nonblocking STM to enable several recent blocking STM optimizations such as timestamp-based validation and ownership
release via store instructions, all leading to a more streamlined and efficient fast path. We present an undo log (eager versioning) variant of our STM, as well as two redo log (lazy versioning) variants, the latter of which are based on the two ownership acquisition techniques (namely eager and lazy) for writes made by transactions.
Experimental results show that our efforts have improved the
performance of nonblocking STMs up to the level of being com
petitive with the state-of-the-art blocking STMs such as TL2.</description>
    <pubDate>Thu, 07 Feb 2008 15:51:08 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/311</guid>
   </item>
  
   <item>
    <title>Amal Fahad: TBD</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/307</link>
    <description>[Friday, March 07, 2008 at  2:00 PM in 703] TBD</description>
    <pubDate>Thu, 07 Feb 2008 15:48:00 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/307</guid>
   </item>
  
   <item>
    <title>Xiaoming Gu: Reuse Distance Distribution in Random Access </title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/306</link>
    <description>[Friday, February 22, 2008 at  2:00 PM in 703] Reuse distance is a basic metric for program locality. The 
distribution of reuse distances, called the reuse signature, shows the average locality or the amount of actively used 
data. Random access is often assumed in analytical models 
about program behavior. An interesting question is whether 
the reuse behavior of random data access has a closed-form 
answer. We prove that the length of reuse distances of random access is uniformly distributed from 0 to n-1; 1 when n is the size of data.

For further reference please refer his MSPC&#39;08  &lt;a href = &quot;http://www.cs.rochester.edu/u/xiaoming/mspc08.pdf&quot;&gt; &lt;FONT COLOR = &quot;BLUE&quot;&gt; position paper. &lt;/FONT&gt; &lt;/a&gt;
</description>
    <pubDate>Thu, 07 Feb 2008 15:47:34 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/306</guid>
   </item>
  
   <item>
    <title>Michael F. Spear: 4th year Graduate Student</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/299</link>
    <description>[Friday, January 25, 2008 at  2:00 PM in 703] Mike will will present work on a new STM algorithm that I developed with Maged Michael and Christoph von Praun while interning at IBM last summer.                                                                                                                                                       
                                                                                                                                                                          
The new algorithm, &quot;RingSTM&quot;, has a fundamentally different approach to transactions; we eschew the use of per-location metadata, instead representing each committed     
transactions by a Bloom filter approximating its write set, and publishing these filters to a single global ring data structure. RingSTM has a number of novel attributes, briefly outlined below:                                                                                                                                       
                                                                                                                                                                          

1 - no read bookkeeping overhead (the state of the art is that every read is logged)

2 - read validation overhead is not linear in the number of reads but in the number of committing writers, with the possibility for strong guarantees on total                                                                                         
validation overhead 

3 - only one atomic operation (the state of the art is one atomic operation per location written)                                                     

4 - livelock freedom 

5 - short critical sections favorable to thread-level speculation                                                                                    

6 - simplified contention management requirements 

7 - strong linearization guarantees                                                                                     

8 - low memory ordering requirements


9 - privatization safety                                                                                                             
                                                                                                                                                                          

In addition to being a novel design with good performance and strong theoretical properties, RingSTM has important implications for hardware design, fine-grained implicit parallelism (like Chen&#39;s BOP), and transactions in the operating system.</description>
    <pubDate>Thu, 24 Jan 2008 09:47:13 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/299</guid>
   </item>
  
   <item>
    <title>Chen Ding: IITK kanpur workshop Trip Report</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/296</link>
    <description>[Friday, January 11, 2008 at  2:00 PM in 703] In this talk Prof. Chen Ding will give us a Trip report on  a workshop on multithreading he attended at Kanpur, India.
http://www.cse.iitk.ac.in/users/mtworkshop07/</description>
    <pubDate>Fri, 11 Jan 2008 10:22:16 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/296</guid>
   </item>
  
   <item>
    <title>Chuanpeng Li: &quot;GPFS Performance Monitoring and Problem Identification</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/291</link>
    <description>[Friday, December 07, 2007 at  2:00 PM in 703] Chuangpeng is a 6th year graduate student. In this talk he will give a general overview of parallel file systems and  present work from his internship on performance monitoring and problem isolation in IBM&#39;s GPFS.</description>
    <pubDate>Thu, 06 Dec 2007 20:54:22 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/291</guid>
   </item>
  
   <item>
    <title>Arrvindh Shriraman: FlexTM: Decoupled Hardware Mechanisms for TM and more</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/284</link>
    <description>[Friday, November 30, 2007 at  2:00 PM in 703] In this talk Arrvindh will describe a set of hardware mechanisms.</description>
    <pubDate>Tue, 13 Nov 2007 15:12:22 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/284</guid>
   </item>
  
   <item>
    <title>Michael F. Spear: Bloom Filters for Fun and STMs</title>
    <link>http://www.cs.rochester.edu/dept/seminar/view/289</link>
    <description>[Friday, November 16, 2007 at  2:00 PM in 703] Mike&#39;s research has mainly focused on developing techniques to speed-up STMs. In this talk, he will describe the basic theory behind Bloom Filters and use them to develop aids for STMs.</description>
    <pubDate>Tue, 13 Nov 2007 15:11:32 -0500</pubDate>
    <guid>http://www.cs.rochester.edu/dept/seminar/view/289</guid>
   </item>
  
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