U. Texas, Austin
Technology trends have caused historical rates of processor performance growth to slow appreciably. Future processors must rely on parallelism at many levels, while tolerating on-chip wire delays and keeping power at manageable levels. In this talk, I will describe the UT-Austin TRIPS prototype, which is based on a new, post-RISC class of instruction set architectures called Explicit Data Graph Execution (or EDGE). By exploiting the features of the EDGE ISA, each TRIPS prototype chip contains two 16-wide out-of-order issue cores, each with a 1,024 instruction execution window. A TRIPS processor contains seven distinct microarchitectural networks (or micronets), used to provide wire-scalable on-chip communication. I will conclude the talk by outlining a second-generation microarchitecture, called TMAX, based on the TRIPS ISA that solves the two challenges of adaptive processor granularity and supersized load-store queues.
Doug Burger is an associate professor of computer sciences at the University of Texas. He co-leads the TRIPS project, aimed at building general-purpose microprocessors that sustain high levels of parallelism. He received his Ph.D. from the University of Wisconsin in 1998.