Abstract: The need for computational power has increased with emerging workloads such as artificial intelligence driving the information economy. Yet data center and embedded computing alike desire reduced power consumption. With the breakdown of semiconductor technology scaling, we no longer attain improved performance and reduced energy consumption by using smaller transistors. The semiconductor industry has resorted to hardware specialization as a means to provide the performance and energy benefits consumers have experienced since the invention of the microprocessor. However, specialized hardware units introduce new challenges, namely -- what to specialize, how to specialize and how to integrate specialized units. Current approaches require manual effort to analyse, restructure and rewrite workloads to take advantage of specialized hardware accelerators.
In my talk, I will identify the challenges in building and utilizing hardware accelerators for evolving software workloads. I will describe a two pronged approach to architectural specialization. First, a top down approach uses program analysis to determine code regions amenable for specialization. I have implemented a prototype compiler toolchain to automatically identify, analyze, extract and grow code segments which are amenable to specialization in a methodical manner. Second, a bottom up approach evaluates particular hardware enhancements to enable the efficient data movement of specialized regions. We have devised and evaluated coherence protocols and flexible caching mechanisms to reduce the overhead of data movement within specialized regions.
I will focus on the former, workload centric approach, which analyses large, irregular programs at the path granularity. We enumerate static and dynamic program characteristics precisely with low overhead. We analyse the potential for performance and energy improvement via specialization at the path granularity. We develop mechanisms to extract and merge amenable paths into larger segments. They are constructed from the observation that oft-executed program paths have the same start and end point. This allows for increased offload opportunity while retaining the same interface for specialization. Finally, I will describe how the hardware centric approach complements the automated extraction of specialized units and discuss future research directions.
Bio: Snehasish Kumar received his PhD from Simon Fraser University, Canada. His dissertation focuses on application specific hardware specialization to mitigate the impact of the breakdown of Moore's law. During his graduate career he has published his work at premier computer architecture venues such as ISCA, MICRO and HPCA. His research spans across cache memory systems, coherence protocols, workload characterization and automated identification and extraction of hardware accelerators.