In this talk, I will present a number of our proposed architectural designs to reduce the performance synchronization overhead from warp criticality and to scavenge performance gains by explicitly considering the unique latency tolerance feature of GPUs and with intelligent memory hierarchy designs. We design a coordinated solution, named criticality-aware warp acceleration (CAWA—ISCA2015) that efficiently manages compute and memory resources to accelerate the critical warp execution. Specifically, we design (1) a criticality predictor to identify critical warps in a thread block, (2) a criticality-aware warp scheduler that preferentially allocates more time resources to the critical warp, and (3) a criticality-aware cache reuse predictor that assists critical warp acceleration by retaining latency-critical, useful data in the cache. Our evaluation results show that CAWA improves GPGPU performance by an average of 23% while state-of-the-art schedulers such as GTO and 2-level scheduler, improve performance by 16% and -2%, respectively. Then, I will talk about our designs tailored for the GPU memory subsystems for high performance and high energy efficiency delivery, which can further improve the performance of cache-sensitive GPGPU applications by an average of over 40% (ID-Cache—IISWC2016, Ctrl-C—ICCD2016, and LATTE-C). To continue the performance scaling with GPUs, we propose a multi-chip-module GPU architecture (MCM-GPU—ISCA2017) with three important architectural optimizations that significantly improve the data locality in the GPU modules. Our evaluation shows the optimized MCM-GPU architecture achieve 23.7% speedup and 81.8% inter-GPU-module bandwidth reduction. Our optimized MCM-GPU architecture is 29.4% faster than an equally equipped multi-GPU system.
In addition to high capacity computing, personalized computing has gained increasing attention. I will also touch upon our on-going research efforts in this domain and present our vision for mobile performance quality, temperature, and energy efficiency optimization with statistical performance prediction and advanced cooling technologies. Our statistical modeling framework for application execution time are within 99.34% of the measured values. We show that, on an actual Qualcomm Snapdragon 8074 mobile chipset, our proposed energy efficiency controller achieves a 29% power saving over commonly-used Linux governors while maintaining an average web page load time of 2 seconds with a likelihood of 90%.
Carole-Jean Wu is an Assistant Professor of Computer Science and Engineering in the School of Computing, Informatics, and Decision Systems Engineering in Arizona State University. She is the director of the Energy Efficient Computer Architecture Laboratory and she is also affiliated with the NSF I/UCRC Center for Embedded Systems (CES). Prof. Wu receives her M.A. and Ph.D. in Electrical Engineering from Princeton University in 2008 and 2012, and a B.Sc. degree in Electrical and Computer Engineering from Cornell University. Before joining ASU, Prof. Wu held a number of internship positions with Intel, IBM, and Google.
Prof. Wu works in the area of Computer and System Architectures. In particular, her research interests include high-performance and energy-efficiency computer architectures through hardware heterogeneity, energy harvesting techniques for emerging computing devices, temperature and energy management for portable electronics, performance characterization, analysis and prediction, and memory subsystem designs. Prof. Wu is the recipient of the 2017 NSF CAREER Award, the 2017 IEEE Phoenix Section Young Engineer of the Year Award, the 2014 IEEE Best of Computer Architecture Letter Award, the 2013 Science Foundation of Arizona Bisgrove Early Career Award, and the 2011-12 Intel Ph.D. Fellowship Award. Her research has been supported by both industry partners and the National Science Foundation.