High density and low cost have been considered as the first-priority optimization goal for commodity DRAM. As memory technology continues to scale (“More Moore”), energy efficiency has become a pressing issue. DRAM energy consumption contributes a significant part of the system total energy. Row activation is one of the most energy inefficient components in DRAM. Prior work on reducing DRAM row activation energy relies on increasing the number of local wires to avoid performance degradation, which adds unaffordable area overheads. This talk will present our recent work on interleaved I/O, which allows data transferring from different partially activated banks to share the global I/O. The proposed DRAM architecture enables half-, quarter-, or one-eighth- page activations without adding wires. The second part of the talk will introduce our on-going work on supporting emerging memory features (“More than Moore”). The last decade has seen an explosion in new and innovative memory technologies. While certain technologies, like transactional memory, have seen adoption at the language level, others, such as sandboxed memory, scratchpad memory, and persistent memory, have not received systematic support. Our on-going work aims to provide unified system supports to enable easy adoption and fast prototype of emerging memory features.
Xiaochen Guo is an Assistant Professor in the Department of Electrical and Computer Engineering at Lehigh University. Dr. Guo received her Ph.D. degree in Electrical and Computer Engineering from the University of Rochester in 2015, and B.S. degree from Beihang University in 2009. Dr. Guo's research interests are in the broad area of computer architecture, with an emphasis on leveraging emerging technologies to build energy-efficient architectures. Dr. Guo is a recipient of IBM Ph.D. Fellowship, P. C. Rossin Assistant Professorship, the National Science Foundation CAREER Award, and the Lawrence Berkeley National Laboratory Computing Sciences Research Pathways Fellowship.