Login
Computer Science @ Rochester
Friday, November 13, 2009
2:00 PM
Computer Studies Bldg. Room 703
Peng Liu
Zhe Jiang University
Hardware Transactional Memory Architecture and Emulation Platform
Abstract: As computer industry comes into the era of parallel processing period, the difficulty of parallel programming has become prominent. In addition, multithreaded execution requires synchronization for accessing shared memory. The Hardware Transactional Memory (HTM) project provides an advanced mechanism that can allow programmers to define parallel transactions executed in an atomic way and thus simplify the concurrency management in programming. Due to the low efficiency of traditional software simulators, a promising hardware-based prototype would be developed in order to emulate such a chip multi-processors system with HTM support. The Transactional-memory Emulation Accelerator (TEA) is such a hardware platform that used in the project built from field programmable gate array (FPGAs). A brief introduction to the design strategy of TEA is given.