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Computer Science @ Rochester
Friday, November 05, 2010
2:00 PM
Computer Studies Bldg. Room 703
Roberto Gioiosa
University of Rochester
Improving efficiency of high performance systems by dynamic hardware resource allocation
Current Chip Multi-Processors (CMPs) dominates the market (from embedded systems to large scale machines). These systems run complex dynamic workload that share underlying hardware resource. Given the complexity of these systems and their workload, hardware-only or software-only resource allocation may not deliver optimal performance. As a result, current parallel workloads are not experiencing the speedup that was promised at the beginning of the multi-core era. Co-designed hardware/software dynamic hardware resource allocation may, instead, provide higher performance/watt ratio. In this scenario, hardware and software cooperate to reach their final goal. The processors architecture expose to the software hardware mechanisms for controlling the allocation of processor's internal resources. On the other hand, software can more efficiently track applications' behavior and assign hardware resource accordingly to applications' needs. To close the circle, hardware provides feedbacks on application's progress. Current multi-core processors, like recent IBM POWER architectures, provides dynamic hardware resource allocation mechanisms. We use some of them to explore the effectiveness our hardware/software resource allocation approach.

In this talk I will go through to examples where dynamically assigning hardware resource provides benefits. The first case is load imbalance for HPC applications. Load imbalance may cause significant performance degradation, which becomes larger as the number of processes in a supercomputer increases. Inside a single node of a cluster, load imbalance can be reduced by effectively assigning hardware resources to accordingly to the application's computation power requirements. Dynamic resource assignation allows reducing the imbalance in parallel applications, transparently to the user, by controlling task's speed and, hence, reducing the total execution time. Load imbalance depends on several run-time factors, including system and the application input-set, therefore, it is desirable for a load balancing mechanism to be transparent to the user and automatic. We implemented a dynamic process scheduler for the Linux kernel (HPCSched) that automatically and transparently balances HPC applications according to their behavior. Our results show that our proposal leads to a consistent performance improvement for one of the NAS benchmark and for a real HPC application (much more dynamic than the benchmark). Our results also show that, if resource allocation is not used properly, the imbalance of applications is worsened causing performance loss.

The second test case is an analysis of performance/power efficiency on a state-of-the-art multi-core/multi-thread system. Controlling power consumption and temperature is of major concern for modern computing systems. In this study we show that static decisions on whether to consolidate tasks into the same core/chip may be improved by dynamically considering the low-power capabilities of the underlying architecture, the characteristics of the workload and by dynamically assigning resources. Our preliminary results shows up to 5X improvement in ED2P.