Login
Computer Science @ Rochester
Tuesday, May 02, 2006
11:00 AM
CSB 209
Ph.D. Thesis Proposal
Virendra J. Marathe
University of Rochester
Improving the Usability of Transactional Memory
The age of parallel programming is here. With major microprocessor vendors going the multi-core chip way it is clear that every programmer will have to write parallel programs, a specialty of only the few talented programmers. Conventional lock based approach is too hard, and ad hoc nonblocking techniques are even harder. Transactional Memory (TM), a programming paradigm borrowed from databases, is the only hope for near future. TM promises to relieve the programmer from the hard task of reasoning about concurrency issues. However, the TM technology is far from mature for deployment in mainstream applications. Several issues related to efficiency, semantics, programming abstraction, language support, etc. need to be resolved. In this thesis we hope to address some of these issues.

Beginning with some background review, we elaborate on our recent contributions in runtime support for TM. This work includes design space analysis, workload adaptivity, and design of a new hardware-software hybrid system. We have implemented five different systems, and several variants of two systems in this process. We also present our work on enhancements to transactional semantics. Our semantic extensions enable concurrent transactions interact with each other. We thereafter propose our preliminary ideas on the issues of support for nesting, conditional waiting, irrevocable side-effects, lower overhead nonblocking progress guarantees, better programming abstractions, safe optimizations, and cleaner transaction interactions. This thesis work will focus on refining our ideas and building concrete infrastructures for their evaluation.