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Computer Science @ Rochester
Thursday, May 03, 2007
3:00 PM
Computer Science Bldg. Room 601
Ph.D. Thesis Proposal
Arrvindh Shriraman
University of Rochester
"Architectural Support for Memory Monitoring and Data Isolation in Shared-Memory Multiprocessors"
Increasing chip density and power limitations has forced hardware manufacturers to embrace hardware parallelism for all application domains. New programming models such as transactional memory and speculative execution seek to ease the task of writing multithreaded code and enable high utilization of these chips. My proposal addresses the challenge of mainstream parallelism by identifying performance-critical operations across these programming models and then accelerating or simplifying them using architectural mechanisms.

As part of our on-going effort, we have targeted transactional memory. In transactional memory, programmers mark regions of code as transactional and the underlying runtime system guarantees atomicity, isolation, and consistency of data while exploiting available concurrency using speculative execution. We have developed two complementary architectural mechanisms for accelerating transactions (1)Alert-on-update (AOU), which leverages cache coherence for event-based communication, and (2)Programmable data isolation (PDI), which allows a processor to hide local writes for speculation until software chooses to make them visible. These mechanisms enabled us to build a hardware-software based flexible transactional memory (TM) system, ``RTM'', that could accelerate bounded size transactions and exploit software controlled policies.

We will explore extensions to our current system, which will include (1)crafting and defining memory system behavior under various execution histories, (2)extending the cache protocol state machine to explore scalability of our techniques in large scale multiprocessors, (3)comparison with a hardware TM system, and (4)building a prototype of the base bus based protocol in FPGA.

The memory subsystem is an important resource that cannot be used efficiently if hardware provides only read and write primitives. Current architectures do not provide a fine-grained, low-overhead mechanism for software to either observe memory operations of remote processors or control the visibility of local writes. To this end, we will extend our AOU and PDI mechanisms to handle tasks that are unbounded in size and time. We explore the following mechanisms: a "conflict table" that tracks remote concurrent writes and reads in a multiple-writer coherence system, and exports this information to the software; thread local "overflow buffers" that (1)maintain the access permissions and data for monitored and isolated lines that have been evicted from the private cache and (2)provide access to the buffered overflowed lines transparent to application software. We aim to utilize these hardware mechanisms to build a TM system in which overflow of available hardware resources results in graceful degradation while still using software to monitor and control visibility of memory locations.