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Computer Science @ Rochester
Tuesday, April 29, 2008
12:30 PM
Computer Studies Bldg. Room 703
Ph.D. Thesis Proposal
Xiao Zhang
University of Rochester
On-chip Shared Resource Management in the Multicore Era
Because of overwhelming heat concerns, processor manufacturers have shifted to the use of multiple cores on a single chip. One of the key features of this new architecture is that all cores on a single chip share some cache (usually the last level cache) and off-chip bandwidth. This sharing presents new challenges due to the subtle interactions of simultaneously executing processes. For example, processes that are simultaneously accessing the shared cache may conflict with each other and result in skewed performance.

Today's operating systems are oblivious to to the needs of individual process for on-chip resources. Multi-core operating systems must be made aware of on-chip resource competition in order for effective utilization of chip resources. Using hardware performance counter information, it is possible to provide consolidated operating system support to efficiently manage shared on-chip resources, particularly the shared cache and memory bus bandwidth. I will explore both hardware-assisted and OS-level software techniques to improve the performance, fairness, and scalability of multicore systems.