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Computer Science @ Rochester
Wednesday, April 30, 2008
10:00 AM
Computer Studies Bldg. Room 601
Ph.D. Thesis Proposal
Hemayet Hossain
University of Rochester
Effective on-Chip Cache Utilization in Chip Multiprocessors
CMOS scaling trends allow increasing numbers of transistors on a single chip. In order to take advantage of these trends with manageable design complexity while staying within power budgets, processor designers are increasingly turning toward multi-core architectures --- often chip multiprocessors (CMPs) of simultaneous multithreaded (SMT) cores --- for all application domains.

Increasing the number of cores on a single chip leads to higher demand on on-chip cache capacity and interconnect bandwidth (on/off-chip). Scalable cache coherence protocols support a large number of cores by reducing coherence bandwidth requirements (e.g., directory). However, they squander away the low latency cache-cache transfers (possible due to on-chip interconnects) by introducing a level of indirection on the critical path of cache misses. Many commercial, scientific, and data-mining workloads exhibit fine-grain (both temporal and spatial) data-sharing patterns (due to communication and synchronization) and desire low latency core-core data transfers but are penalized by these scalable protocols. Furthermore, their working sets well exceed the private cache sizes and stress-test the shared cache levels.

In this work, we (1) exploit low latency on chip interconnects and (2) improve the utilization of shared caches. First, we super-impose a direct access substrate on an existing scalable protocol to take advantage of low latency interconnects. We show how this mechanism can be used to efficiently support fine-grain sharing in applications. Additional benefits include reduced power consumption and reduced interconnect bandwidth. We address location and placement of data via novel uses of prediction and an adaptive replication, migration, and producer-consumer optimization(ARMCO) cache coherence protocol. Second, to meet the cache capacity demands of multiple cores and to improve the utilization efficiency of on-chip cache resources we propose a sharing-aware adaptive replacement policy (ShARP) and decoupling of tag and data. Finally, we will analyze the effects of technology on, and scaling implications of, the proposed protocol as part of this work.