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Computer Science @ Rochester
Tuesday, August 12, 2008
2:00 PM
Computer Studies Building, Room 601
Virendra Marathe
University of Rochester
Enhancing the Performance and Usability of Software Transactional Memory
Transactional Memory (TM) is an emerging concurrency control technology that promises to significantly ease the difficult task of programming on multicore systems. Foundational work on TM grew out of research in nonblocking concurrent algorithms. Hence early software TM (STM) systems were all nonblocking. However they incurred high overheads, rendering them largely impractical.

More recently, there has been a shift toward blocking implementations of STM. This has been accompanied by several significant performance optimizations, making blocking STMs far more practical. A general hypothesis, based on informal arguments, has emerged that nonblocking STMs are fundamentally slower than blocking STMs. In this talk I will show that this hypothesis is wrongly founded, and that nonblocking STMs can approach the performance of, and even outperform, state-of-the-art blocking STMs. I will present several variants of our most recent nonblocking STM that are competitive with state-of-the-art blocking STMs.