My dissertation addresses resource management issues on multicore chips at the operating system level. Specifically, I introduce three techniques to control resource usage.
First, I propose a hot-page coloring approach that enforces cache partitioning on only a small set of frequently accessed (or hot) pages to segregate most inter- thread cache conflicts. The cost of identifying hot pages online is reduced by leveraging knowledge of spatial locality during a page table scan of access bits. Hotness-based page coloring greatly alleviates the disadvantages of naive page coloring (memory allocation constraint and recoloring overhead) in practice. Second, I demonstrate that resource-aware scheduling on multicore-based SMP platforms can mitigate resource contention. Resource-aware scheduling employs a simple heuristic that can be easily derived from hardware performance counters. It can effectively reduce overall resource contention and achieve better overall system performance. Aside from the benefits of reduced hardware resource contention, it also engages opportunities for CPU power savings and thermal reduction.
Finally, I show how to reuse existing hardware features to control resource usage. I demonstrate a hardware execution throttling (e.g., voltage/frequency scaling, duty-cycle modulation, and cache prefetcher adjustment) based frame- work to effectively control shared resource usage on multicore chips. In addition to resource controlling mechanisms, I also study a variety of resource management policies, including fairness, quality of service, performance, and power, and show how they can be used to guide a selected hardware throttling mechanism.