This significantly upgraded tutorial will cover current and emerging architectural and microarchitectural techniques for both general-purpose and high-end embedded processors. Processor architecture design and evaluation has become exciting, complex, and challenging for both general-purpose and embedded computing -- thanks to increasing performance demands, booming single-chip transistor budgets, and, for embedded processers, programmability, low-cost, and low-power requirements. This tutorial presents the workings of a collection of important recent architectural and micro-architectural techniques for both worlds. For the general-purpose world the focus will be on techniques to exploit instruction-level parallelism (ILP). For embedded processors, some architectural and microarchitectural techniques for reduced code size, configurability, signal processing, etc. will be covered. DSP processor techniques will form a major portion of the embedded processors' coverage in this tutorial. Overall, the tutorial will be a quick but substantive tour of important current and emerging processor techniques.
The attendee is assumed to have the following background:
(i) familiarity with basic computer organization;
(ii) exposure to basic aspects of processor pipelining and
some awareness of microarchitectural techniques (such as
simple 2-bit branch prediction, register renaming, etc.);
(iii) awareness of the basic workings of primary memory
subsystem components such as caches.
20% Beginner, 50% Intermediate, 30% Advanced.
Sriram Vajapeyam is currently with Analog Devices, on leave from a faculty position at the Indian Institute of Science, Bangalore. His primary research interest is processor architecture, with a significant recent research contribution being Trace Processors. Vajapeyam received his Ph.D. in Computer Science from the University of Wisconsin at Madison, and a B.Tech. in Electrical Engineering from the Indian Institute of Technology (IIT), Madras. His previous industry experience includes a year with Cray Research, Inc.
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