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ISCA-2000

June 10-14, 2000
Vancouver, British Columbia, Canada

Advance Program




Saturday, June 10 2000

Workshops/Tutorials  

 

Sunday, June 11 2000

Workshops/Tutorials  

 

Welcome Reception   6:00 p.m. - 8:00 p.m.

    Garden/pool area of the Westin Bayshore Hotel (Salon C in the event of inclement weather)

 

Monday, June 12 2000

 

Keynote   8:30am - 10:00am

    All the Chips Outside: The Architecture Challenge
    Gordon Bell - Microsoft

 

Session 1- Using Threads (chair: Brad Calder, UC San Diego)   10:30am - 12:00noon

    A Scalable Approach to Thread-Level Speculation
    J. Gregory Steffan - Carnegie Mellon University
    Christopher Colohan - Carnegie Mellon University
    Antonia Zhai - Carnegie Mellon University
    Todd Mowry - Carnegie Mellon University

    Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors
    Marcelo Cintra - University of Illinois at Urbana-Champaign
    José F. Martínez - University of Illinois at Urbana-Champaign
    Josep Torrellas - University of Illinois at Urbana-Champaign

    Transient Fault Detection via Simultaneous Multithreading
    Steven K. Reinhardt - The University of Michigan
    Shubhendu Mukherjee - Compaq Computer CorporationA

 

Session 2a - Exploiting Traces (chair: Tom Conte, NC State)   1:30pm - 3:00pm

    Trace Preconstruction
    Quinn Jacobson - Sun Microsystems
    James E. Smith - University of Wisconsin-Madison

    Completion Time Multiple Branch Prediction for Enhancing Trace Cache Performance
    Ryan Rakvic - Carnegie Mellon University
    Bryan Black - Carnegie Mellon University
    John Paul Shen - Carnegie Mellon University

    A Hardware Mechanism for Dynamic Extraction and Relayout of Program Hot Spots ( Slides (pdf))
    Matthew Merten - University of Illinois
    Andrew Trick - University of Illinois
    Erik M. Nystrom - University of Illinois
    Ronald D. Barnes - University of Illinois
    Wen-mei W. Hwu - University of Illinois

 

Session 2b - Modeling Performance and Power (chair: Dirk Grunwald, Colorado)   1:30pm - 3:00pm

    HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs
    Mark Oskin - U.C. Davis
    Frederic T. Chong - U.C. Davis
    Matthew Farrens - U.C. Davis

    Wattch: A Framework for Architectural-Level Power Analysis and Optimizations
    David Brooks - Princeton University
    Vivek Tiwari - Intel Corporation
    Margaret Martonosi - Princeton University

    Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower
    Vijaykrishnan, N. - Penn State Univ
    Kandemir, M. - Penn State
    Irwin, M.J. - Penn State
    Kim, H. S. - Penn State
    Ye, W. - Penn State

 

Session 3 - Memory Hierarchy Improvements (chair: Kourosh Gharachorloo, Compaq)   3:30pm - 5:00pm

    A Fully Associative Software-Managed Cache Design
    Erik G. Hallnor - The University of Michigan
    Steven K. Reinhardt - The University of Michigan

    Recency-based TLB Preloading
    Ashley Saulsbury - Sun Microsystems Laboratories
    Fredrik Dahlgren - Ericsson Mobile Communications AB
    Per Stenström - Chalmers University

    Memory Access Scheduling
    Scott Rixner - Stanford University
    William J. Dally - Stanford University
    Ujval J. Kapasi - Stanford University
    Peter Mattson - Stanford University
    John D. Owens - Stanford University

 

Tuesday, June 13 2000

 

Session 4 - Multiprocessors (chair: Per Stenström, Chalmers)   8:30am - 10:00am

    Selective, Accurate, and Timely Self-Invalidation Using Last-Touch Prediction
    An-Chow Lai - School of Electrical and Computer Engineering, Purdue University
    Babak Falsafi - School of Electrical and Computer Engineering, Purdue University

    An Embedded DRAM Architecture for Large-Scale Spatial-Lattice Computations
    Norman Margolus - MIT Artificial Intelligence Laboratory

    Smart Memories: A Modular Reconfigurable Architecture
    Kenneth Mai - Stanford University
    Timothy Paaske - Stanford University
    Nuwan Jayasena - Stanford University
    Ron Ho - Stanford University
    William J. Dally - Stanford University
    Mark Horowitz - Stanford University

 

Session 5a - Analysis of Workloads and Systems (chair: Antonio González, UPC)   10:30am - 12:00noon

    Understanding the Backward Slices of Performance Degrading Instructions
    Craig Zilles - University of Wisconsin
    Gurindar S. Sohi - University of Wisconsin

    On the Value Locality of Store Instructions
    Kevin Lepak - University of Wisconsin
    Mikko Lipasti - University of Wisconsin

    Performance Analysis of the Alpha 21264-based Compaq ES40 System
    Zarka Cvetanovic - Compaq Computer
    R. E. Kessler - Compaq Computer

 

Session 5b - Customizable Systems (chair: Margaret Martonosi, Princeton)   10:30am - 12:00noon

    Lx: A Technology Platform for Customizable VLIW Embedded Processing
    Paolo Faraboschi - Hewlett-Packard Laboratories
    Joseph Fisher - Hewlett-Packard Laboratories
    Geoffrey Brown - Hewlett-Packard Laboratories
    Giuseppe Desoli - Hewlett-Packard Laboratories
    Fred (Mark Owen) Homewood - ST Microelectronics

    Reconfigurable Caches and their Application to Media Processing ( Slides (ppt))
    Parthasarathy Ranganathan - Rice University
    Sarita Adve - University of Illinois, Urbana-Champaign
    Norman Jouppi - Compaq Western Research Lab

    CHIMAERA: A high performance architecture with a tightly-coupled reconfigurable functional unit
    Alex Zhi Ye- ECE Dept., Northwestern University
    Andreas Moshovos - ECE Dept., Northwestern University
    Scott Hauck - EE Dept., Univeristy of Washington
    Prithviraj Banerjee - ECE Dept., Northwestern University

 

Session 6 - Circuit Considerations (chair: Ravi Nair, IBM)   2:00pm - 3:00pm

    Circuits for Wide-Window Superscalar Processors
    Dana S. Henry - Yale
    Bradley C. Kuszmaul - Yale
    Gabriel H. Loh - Yale
    Rahul Sami - Yale

    Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures
    Vikas Agarwal - The University of Texas at Austin, Department of Computer Sciences
    M.S. Hrishikesh - The University of Texas at Austin, Department of Computer Sciences
    Stephen Keckler - The University of Texas at Austin, Department of Computer Sciences
    Doug Burger - The University of Texas at Austin, Department of Computer Sciences

 

Panel - Slow Wires, Hot Chips and Leaky Transistors: New Challenges in the New Millennium   3:30pm - 5:00pm

    Moderator:
    Shubhendu Mukherjee - Compaq Computer Corporation
    Panelists:
    Bob Colwell - Intel
    Dirk Grunwald - University of Colorado
    Mark Horowitz - Stanford University
    Norm Jouppi - Compaq
    Jim Smith - University of Wisconsin
    T.N Vijaykumar - Purdue University

 

Wednesday, June 14 2000

 

Session 7 - Extracting Parallelism (chair: David Wood, Wisconsin)   8:30am - 10:00am

    Vector Instruction Set Support for Conditional Operations
    James E. Smith - University of Wisconsin-Madison
    Greg Faanes - SGI/Cray Rsch
    Rabin Sugumar - Sun Microsystems

    Instruction Path Coprocessors
    Yuan Chou - ECE Department, Carnegie Mellon University
    John Paul Shen - ECE Department, Carnegie Mellon University

    Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing
    Luiz André Barroso - Compaq
    Kourosh Gharachorloo - Compaq
    Robert McNamara - Compaq
    Andreas Nowatzyk - Compaq
    Shaz Qadeer - Compaq
    Barton Sano - Compaq
    Scott Smith - Compaq
    Robert Stets - Compaq
    Ben Verghese - Compaq

 

Session 8 - Microarchitecture Innovations (chair: Matt Farrens, UC Davis)   10:30am - 12:00noon

    Allowing for ILP in an Embedded Java Processor
    Ramesh Radhakrishnan - UT Austin
    Deependra Talla - UT Austin
    Lizy Kurian John - UT Austin

    Early Load Address Resolution Via Register Tracking
    Michael Bekerman - HAL Computer Systems
    Adi Yoaz - Intel Corporation
    Freddy Gabbay - Mellanox Technologies Inc
    Stephan Jourdan - Intel Corporation
    Maxim Kalaev - Intel Corp
    Ronny Ronen - Intel Corporation

    Multiple-Banked Register File Architectures
    José-Lorenzo Cruz - UPC Barcelona, Departament Arquitectura Computadors
    Antonio González - UPC Barcelona, Departament Arquitectura Computadors
    Mateo Valero - UPC Barcelona, Departament Arquitectura Computadors
    Nigel Topham - Siroyan Ltd.

 


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