CSC252 Assignment 3
Mon Feb 26 11:28:30 EST 1996
In this assignment we will learn how to use the MINT simulator. The assignment requires that we built an interface to the simulator that allows to count the dynamic instruction count of a program. MINT calls user-defined function on certain events. Events can include instructions, read memory references, write memory references and others. By default these functions do nothing and simply tell MINT to continue with the execution of the program. Your responsibility is to modify these functions so as to count the number of instructions executed for each instruction category. The relevant MINT functions are:
For the sim_instr function the field ptask->pevent->vaddr contain the numerical representation of that instruction. You can use the table appended in this document to figure out the type of instruction you have based on the numerical value for that instruction. The table contains the most frequent instruction so it is possible (although not likely) that you will encounter instruction not included in the table. Place these instruction under a miscellaneous category.
After you have built your simulator, use it to count the instructions of the sorting program you wrote in the previous assignment. Which instructions dominate execution? If you had a choice of making each instruction take two clock cycles, or if you could make 10% of the instructions take one clock cycle, and the remaining instruction take four clock cycles which one would you choose? Why?
Start early so you can familiarize yourself with the simulator. The manual can be accessed online under the bibliography link from the course home page. Turn in a short write-up describing your findings, including the frequency of instruction measured, and your design choice for the clock-cycle question. The assignment is due Monday, March 25th.
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ADD 000000 rs rt rd 00000 100000
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ADDI 001000 rs rt immediate
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ADDIU 001001 rs rt immediate
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ADDU 000000 rs rt rd 00000 100001
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AND 000000 rs rt rd 00000 100100
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ANDI 001100 rs rt immediate
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BEQ 000100 rs rt offset
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BEQL 010100 rs rt offset
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BGEZ 000001 rs 00001 offset
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BGEZAL 000001 rs 10001 offset
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BGEZALL 000001 rs 10011 offset
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BGEZL 000001 rs 00011 offset
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BGTZ 000111 rs 00000 offset
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BGTZL 010111 rs 00000 offset
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BLEZ 000110 rs 00000 offset
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BLEZL 010110 rs 00000 offset
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BLTZ 000001 rs 00000 offset
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BLTZAL 000001 rs 10000 offset
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BLTZALL 000001 rs 10010 offset
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BLTZL 000001 rs 00010 offset
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BNE 000101 rs rt offset
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BNEL 010101 rs rt offset
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BREAK 000000 code 001101
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DADD 000000 rs rt rd 00000 101100
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DADDI 011000 rs rt immediate
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DADDIU 011001 rs rt immediate
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DADDU 000000 rs rt rd 00000 101101
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DDIV 000000 rs rt 00000 011110
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DDIVU 000000 rs rt 00000 011111
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DIV 000000 rs rt 00000 011010
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DIVU 000000 rs rt 00000 011011
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DMULT 000000 rs rt 00000 011100
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DMULTU 000000 rs rt 00000 011101
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DSLL 000000 rs rt rd sa 111000
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DSLLV 000000 rs rt rd 00000 010100
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DSRL 000000 rs rt rd sa 111010
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DSRLV 000000 rs rt rd 00000 010110
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DSUB 000000 rs rt rd 00000 101110
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DSUBU 000000 rs rt rd 00000 101111
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J 000010 target
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JAL 000011 target
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JALR 000000 rs 00000 rd 00000 001001
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JR 000000 rs 00000 001000
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MFHI 000000 000000 rd 00000 010000
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MFLO 000000 000000 rd 00000 010010
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MTHI 000000 000000 rd 00000 010001
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MTLO 000000 000000 rd 00000 010011
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MULT 000000 rs rt 00000 011000
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MULTU 000000 rs rt 00000 011001
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NOR 000000 rs rt rd 00000 100111
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OR 000000 rs rt rd 00000 100101
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ORI 001101 rs rt immediate
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SLL 000000 rs rt rd sa 000000
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SLLV 000000 rs rt rd 00000 000100
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SLT 000000 rs rt rd sa 101010
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SLTI 001010 rs rt immediate
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SLTIU 001011 rs rt immediate
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SLTU 000000 rs rt rd sa 101011
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SRL 000000 rs rt rd sa 000010
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SRLV 000000 rs rt rd 00000 000110
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SUB 000000 rs rt rd 00000 100010
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SUBU 000000 rs rt rd 00000 100011
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XOR 000000 rs rt rd 00000 100110
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XORI 001110 rs rt immediate