Processor Design: DataPath and Control
DataPath for a single cycle processor
The image above shows the datapath for a simple single-cycle CPU. The
program counter feeds the instruction memory with an address and an
instruction is generated. Part of the instruction is fed to the
register file and determines which registers need to be accessed by
the instrcution. The output of the register file is fed to the ALU
and the result (if necessary) is passed to the date memory unit. In a
bit more detail the datapath shown accomodates three types of
instructions: Arithmetic/Logical Instructions, Memory Reference
Instructions, Control Flow Instructions.
The DataPath access for each type of instruction is as follows:
- Arithmetic/Logical Instructions: The instruction is generated by
the Instruction Memory. We use the instruction to read the two
regsiters it reads data from out of the Register file. The values of
these two registers are fed to the ALU and the selected operation is
performed on them. The result is stored in the register that is also
selected by the instruction. The PC is set to PC plus 4.
- Memory Reference Instructions: The instruction is generated by
the Instruction Memory. We use the instruction to read the one
register that contains the base address. The ALU is then used to add
the base address and the 16-bit offset that is part of the
instruction. The result of the ALU is passed to the data memory as
the address that the memory operation will reference. If the
operation is a store the data comes from the Register file and is
written to the Data Memory. If it is a load the data is produced by
the Data Memory and is written to the Register file. The PC is set to
PC plus 4.
- Control Flow Instructions: (I only discuss the beq instruction)
The instruction is generated by the Instruction Memory. We use the
instruction to read the two register the contain the values that we
are comparing. The least significant 16 bits of the instruction are
added to the current PC. The ALU performs a subtract to the values we
are comparing and uses the result to drive the multiplexor that feeds
the PC. If the result is 0 then the PC is set to the old PC plus the
branch offset, otherwise the PC is set ot the old PC plus 4.
Obviously there needs to be some amount of control to make sure the
ALU does the right operation, and the multiplexors allow the correct
operand to propagate. The control logic is also derived from the
instruction.
What is Wrong with a Single Cycle Implementation?
Since the clock cycle has to be the same length for every instruction,
the clock cycle is dictated by the longest instruction. This happens
to be a load instruction which accesses the instruction memory, the
register file, the ALU, the data memory, and then register file, in
that order. Brach instructions which only need to access the
instruction memory, the register file, and the ALU will take just as
long.
A Multiple cycle implementation will use a single clock to drive each
individual functional unit and each instruction takes a number of
clock cycles equal to the number of functional units it utilizes.
Exceptions
The CPU described above functions assuming every instruction does
something correct. However programs are often incorrect and thus we
need to check for mistakes (i.e. illegal instructions, arithmetic
overflow, etc.) and handle them. This is done using the exception
mechanism. In a nutshell the exception mechanism is a piece of logic
that determines that something went wrong and sets the PC to a
predetermined address where the exception handler lives. The
exception handler is a piece of software that saves the state of the
machine (registers) and then services the exception. In many cases
servicing an exception implies killing the program that generated it.