Lingxiang XiangPhD Candidate
Department of Computer Science
University of Rochester
Office: CSB 615
Email: lxiang [at] cs.rochester.edu
I am a third year graduate student, working under the supervision of Prof Michael Scott in the system group. Prior to coming here, I got my BS and MS degrees in Computer Science, both from Zhejiang University, China.
My research interests lie in enhancing the interaction between software and hardware. In the past few years, I have been working in new cache designs based on program behavior, as well as power-aware computing.
Publications (click a paper's title to see its abstract)
Compiler Aided Manual Speculation for High Performance Concurrent Data Structures (pdf)
by Lingxiang Xiang and Michael L. Scott
In 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'13), Shenzhen, China, Feb. 2013.
Speculation is a well-known means of increasing parallelism among concurrent methods that are usually but not always independent. Traditional nonblocking data structures employ a particularly restrictive form of speculation. Software transactional memory (STM) systems employ a much more general---though typically blocking---form, and there is a wealth of options in between.
Using several different concurrent data structures as examples, we show that manual addition of speculation to traditional lock-based code can lead to significant performance improvements. Successful speculation requires careful consideration of profitability, and of how and when to validate consistency. Unfortunately, it also requires substantial modifications to code structure and a deep understanding of the memory model. These latter requirements make it difficult to use in its purely manual form, even for expert programmers. To simplify the process, we present a compiler tool, CSpec, that automatically generates speculative code from baseline lock-based code with user annotations. Compiler-aided manual speculation keeps the original code structure for better readability and maintenance, while providing the flexibility to chose speculation and validation strategies. Experiments on UltraSPARC and x86 platforms demonstrate that with a small number annotations added to lock-based code, CSpec can generate speculative code that matches the performance of best-effort hand-written versions.
Task Static Single Assignment (T-SSA) and Its Use in Safe Program Parallelization (pdf)
by Chen Ding and Lingxiang Xiang
In The Second Asia-Pacific Programming Languages and Compilers Workshop in conjunction with the International Symposium on Code Generation and Optimization (CGO) , Shenzhen, China, Feb. 2013.
The mechanism of copy-on-write is recently used in speculative and deterministic parallel systems. In these systems, copy-on-write happens when a task modifies a variable for the first time. At the program level, the copying is a form of renaming. This paper extends the formalism of static single assignment (SSA) to introduce a program representation called task static single assignment (T-SSA). The new representation integrates the copy-on-write renaming across tasks with the conventional SSA renaming within a task. This position paper defines the T-SSA form and demonstrates its use in making copy-on-write explicit, automatic, and automatically enhanced for safe program parallelization.
MSpec: A Design Pattern for Concurrent Data Structures (pdf)
by Lingxiang Xiang and Michael L. Scott
In 7th ACM SIGPLAN Wkshp. on Transactional Computing (TRANSACT), New Orleans, LA, Feb. 2012.
Speculation is a well-known means of increasing parallelism among concurrent methods that are usually but not always independent. Traditional nonblocking data structures employ a particularly restrictive form of speculation. Software transactional memory (STM) systems employ a much more general—though typically blocking—form, and there is a wealth of options in between.
We explore data-structure-specific speculation as a design pattern for concurrent data structures. Using several different structures as examples, we consider issues of safety (sandboxing), validation mechanism, and granularity of locking. We note that it can sometimes be useful to perform validation and locking at different granularities. Through experiments on UltraSPARC and x86 platforms, we demonstrate that MSpec can lead to highly efficient algorithms, particularly in methods with a significant search component.
Less Reused Filter: Improving L2 Cache Performance via Filtering Less Reused Lines (pdf)
by Lingxiang Xiang, Tianzhou Chen, Qingsong Shi and Wei Hu
In 23rd International Conference on Supercomputing (ICS'09), New York, USA. Jun. 8-12, 2009.
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines that are never reused or reused for few times. In this case, the cache performance can be improved through retaining a portion of working set in cache for a period long enough. Previous schemes approach this by bypassing never reused lines. Nevertheless, severely constrained by the number of never reused lines, sometimes they deliver no benefit due to the lack of never reused lines.
This paper proposes a new filtering mechanism that filters out the less reused lines rather than just never reused lines. The extended scope of bypassing provides more opportunities to fit the working set into cache. This paper also proposes a Less Reused Filter (LRF), a separate structure that precedes L2 cache, to implement the above mechanism. LRF employs a reuse frequency predictor to accurately identify the less reused lines from incoming lines. Meanwhile, based on our observation that most less reused lines have a short life span, LRF places the filtered lines into a small filter buffer to fully utilize them, avoiding extra misses.
Our evaluation, for 24 SPEC 2000 benchmarks, shows that augmenting a 512KB LRU-managed L2 cache with a LRF having 32KB filter buffer reduces the average MPKI by 27.5%, narrowing the gap between LRU and OPT by 74.4%.
Balance the Battery Life and Real-time Issues for Portable Real-time Embedded System by Applying DVS with Battery Model (link)
by Chen Tianzhou, Huang Jiangwei, Xiang Lingxiang and Wu Xinliang
In 34th Annual Conference of the IEEE Industrial Electronics Society (IECON'08). Orlando, Florida, USA. Nov. 10-13, 2008.
An Anonymous R2D2 Robot 2013
This is a birthday gift I built from scratch for my girlfriend. The hardware is made of a broken Interactive R2D2 toy and a bunch of cheap parts purchased online. Inside, the little guy is powered by a Raspberry Pi running Rasbian. It supports a rich set of features, including voice control (in English and Chinese, using PocketSphinx), face recognition (using OpenCV), motion detection, ultrasonic distance detection, audio message record and replay, sound play and TTS, rechargeable battery, wifi and so on.
Compiler Aided Manual Speculation 2011-2012
It's a research project which began as a CSC 400 course project in 2010 and finally turned out as my PPoPP'13 paper.
Source code will be available soon.
Others before 2010
I've done a few projects including a MIPS simulator and two games when I was a undergraduate student. Follow this link (in Chinese) for details.
Life Outside Work
I spend most of my spare time reading. I maintain a life-long reading list for myself, hoping that it could be finished as early as possible so I could start another life happily. I am also a big fan of Woody Allen's movies and the longest run cartoon series, the Simpons.