Dynamically Trading Frequency for
Complexity in a GALS MicroprocessorPDF
S. Dropsho, G.
Semeraro, D.H. Albonesi, G. Magklis and M.L. Scott. 37th Intl Symp
on Microarchitecture (MICRO-37), pp. 157-168, Portland, OR,
Dec 2004.
The Energy Impact of Aggressive
Loop FusionPDF
Y.-K. Zhu,
G. Magklis, M.L. Scott, C. Ding and D.H. Albonesi.
13th Intl Conf on Parallel Architectures and Compilation
Techniques (PACT-13), pp. 153-164, Antibes Juan-les-Pins,
France, Sep/Oct 2004.
(online version corrects accidental
interchange of labels in published paper)
Hiding Synchronization Delays in a
GALS Processor MicroarchitecturePDF
G. Semeraro,
D.H. Albonesi, G. Magklis, M.L. Scott, S. Dropsho
and S. Dwarkadas. 10th Intl Symp on Asynchronous Circuits
and Systems (ASYNC-10), pp. 159-169, Hersonissos, Greece, Apr
2004.
Dynamic Frequency
and Voltage Scaling for a Multiple Clock Domain
MicroprocessorPDF
G. Magklis, G. Semeraro,
D.H. Albonesi, S.G. Dropsho, S. Dwarkadas, and
M.L. Scott. IEEE Micro, Special Issue: Top Picks from
Computer Architecture, 23(6), pp. 62-68, IEEE Computer Society,
Nov/Dec 2003.
Dynamically Tuning Processor
Resources with Adaptive ProcessingPDF
D.H. Albonesi, R. Balasubramonian, S.G. Dropsho,
S. Dwarkadas, E.G. Friedman, M.C. Huang,
V. Kursun, G. Magklis, M.L. Scott, G. Semeraro,
P. Bose, A. Buyuktosunoglu, P.W. Cook, and
S.E. Schuster. Computer, Special Issue on Power-Aware
Computing, 36(12), pp. 49-58, IEEE Computer Society, Dec 2003.
Improving Application Performance
by Dynamically Balancing Speed and Complexity in a GALS
MicroprocessorPDF
G. Semeraro, D.H. Albonesi, S. Dropsho,
G. Magklis, and M.L. Scott. 2nd Workshop on Apllication
Specific Processors (WASP-2), San Diego CA, Dec 2003.
Profile-based Dynamic
Voltage and Frequency Scaling for a Multiple Clock Domain
ProcessorPDF
G. Magklis, M.L. Scott,
G. Semeraro, D.H. Albonesi, and S. Dropsho. 30th
Intl Symp on Computer Architecture (ISCA-30), pp. 14-25, San
Diego CA, Jun 2003.
Dynamic Frequency and Voltage
Control for a Multiple Clock Domain MicroarchitecturePDF
G. Semeraro,
D.H. Albonesi, S.G. Dropsho, G. Magklis,
S. Dwarkadas, and M.L. Scott. 35th Annual Intl Symp on
Microarchitecture (MICRO-35), pp. 356-367, Istanbul, Turkey,
Nov 2002.
Integrating Adaptive On-Chip
Storage Structures for Reduced Dynamic PowerPDF
S. Dropsho,
A. Buyuktosunoglu, R. Balasubramonian, D.H. Albonesi,
S. Dwarkadas, G. Semeraro, G. Magklis, and
M.L. Scott. 11th Intl Conf on Parallel Architectures and
Compilation Techniques (PACT-11), pp. 141-152,
Charlottesville VA, Sep 2002.
Energy Efficient Processor Design
Using Multiple Clock Domains with Dynamic Voltage and Frequency
ScalingPDF
G. Semeraro, G. Magklis, R. Balasubramonian,
D.H. Albonesi, S. Dwarkadas, and M.L. Scott. 8th
Intl Symp on High-Performance Computer Architecture (HPCA-8),
pp. 29-40, Cambridge MA, Feb 2002.
Interweave: Object Caching Meets
Software Distributed Shared Memory
M.L. Scott
et al. ACM SIGOPS Operating Systems Review, 34(2),
pp. 32, Apr. 2000.
On Using Network RAM as a
non-volatile Buffer
D. Pnevmatikatos,
E.P. Markatos, G. Magklis and S. Ioannidis. Cluster
Computing, Special Issue on I/O in Shared-Storage Clusters,
2(4), pp. 295-303, Baltzer Science Publishers BV, 1999.
On Using Reliable Network RAM in
Networks of Workstations
S. Ioannidis,
A.E. Papathanasiou, G.I. Magklis, E.P. Markatos,
D.N. Pnevmatikatos and J. Sevaslidou. Parallel and
Distributed Computing Practices, Special Issue on Cluster
Computing, 2(2), pp. 205-213, Nova Science Publishers, USA, Jun
1999.
On Using Reliable Network RAM in
Networks of Workstations
S. Ioannidis,
A.E. Papathanasiou, G. Maglis, E.P. Markatos,
D. Pnevmatikatos and J. Sevaslidou. Cluster
Computing, pp. 109-121, Chapter 10, ISBN 1-59033-113-3, Nova
Science Publishers, USA, 2001.
Improving Application Performance
by Dynamically Trading Frequency for Complexity in a GALS
Microprocessor
G. Semeraro, D.H. Albonesi,
S. Dropsho, G. Magklis and M.L. Scott. TR 832,
University of Rochester, Computer Science, Feb 2004.
The Energy Impact of Aggresive Loop
Fusion
Y. Zhu, G. Magklis, M.L. Scott,
C. Ding, D.H. Albonesi. TR-822, University of Rochester,
Computer Science, Dec 2003.
The Implementation of
Cashmere
R. Stets, D. Chen,
S. Dwarkadas, N. Hardavellas, G.C. Hunt,
L. Kontothanassis, G. Magklis, S. Parthasarathy,
U. Rencuzogullari, M.L. Scott. TR-723, University of
Rochester, Computer Science, Dec 1999.
On Using Network RAM as a
non-volatile Buffer
D. Pnevmatikatos,
E.P. Markatos, G. Maglis, and S. Ioannidis. TR-227,
ICS-FORTH, Aug 1998.
Issues in the Design and
Implementation of User-Level DMA
E.P. Markatos,
M.G.H. Katevenis, G. Kalokerinos, G. Maglis,
G. Milolidakis, T. Oikonomou. TR-182, ICS-FORTH, Jun
1997.