Pengcheng Li

Projects (only list projects done by me)

LDetector: A Precise (no false-alarms) and Efficient (performance and memory) GPU Race Detector
  • Please refer to WoDet'14
  • Duration period: 11/2013 to now
  • Abstract: Data race detection becomes an important problem in GPU programming. The paper presents a novel solution mainly aimed at detecting data races happening in shared memory accesses with no use of atomic primitives. It makes use of compiler support to privatize shared data and then at run time parallelizes data race checking. It has two distinct features. First, unlike previous existing work, our work gets rid of per memory access monitoring by data privatization technique, which brings a very low performance overhead and also well scalability. Second, data race checking utilizes massively parallel resources on GPU. Preliminary results show two orders of magnitude performance improvement over an existing work


L-Live (Java): Window-based Object Lifetime Behavior Analysis for Java Programs
  • Please refer to ISMM'14, MSPC'14, MSPC'13
  • Duration period: 10/2012 to now
  • Abstract: Most of today's programs make use of a sizable heap to store dynamic data. To characterize the heap dynamics, this paper presents a set of metrics to measure the average amount of data live and dead in a period of execution. They are collectively called average liveness. The paper defines these metrics of average liveness, gives linear-time algorithms for measurement, and discusses their se in finding the best heap size. The algorithms are implemented in a Java tracing system called ElephantTracks and evaluated using the DaCapo benchmarks running on the Oracle HotSpot and IBM J9 Java virtual machines


LSpara: A Success-or-Fail Speculative Parallelization Mechanism for Array Oriented Programs
  • Duration period: 05/2014 to 08/2014 (Summer Internship)
  • Collaborated with NEC American Laboratories at Princeton, copyright @ NEC
  • Abstract: Many scientific and commercial applications expose characteristics of regularities of arrays. To be short, the most time consuming part of them is a section of array-based codes, usually with loops surrounded. This work aims to resolve and exploit parallelism in such sequential codes. Two observations are obtained: 1) either arrays have loop-carried dependence at any iteration; 2) or arrays have no loop-carried dependence at all. Based such observations, this work takes advantage of speculative parallelization idea by keeping tracks of dependence rather than fined-grained dependence like transaction memory. If dependence found, rollback the execution. It would otherwise succeed. We call it a success-or-fail speculative parallelization mechanism. This design achieves very low overhead exploitation of parallelism hidden inside sequential loop codes


LDecorate: Static Code Layout Optimization Built on Strong Linked-path Affinity Hierarchy
  • Collaborated with Futurewei (Huawei U.S. Research Lab at Santa Clara), please refer to ICPP'14
  • Duration period: 06/2013 to 08/2013 (Summer Internship)
  • Abstract: Code layout optimization seeks to reorganize the instructions of a program to better utilize the cache. On multicore, parallel executions improve the throughput but may significantly increase the cache contention, because the co-run programs share the cache and in the case of hyper-threading, the instruction cache. In this paper, we extend the reference affinity model for use in whole-program code layout optimization. We also implement the temporal relation graph (TRG) model used in prior work for comparison. For code reorganization, we have developed both function reordering and inter-procedural basic-block reordering. We implement the two models and the two transformations in the LLVM compiler. Experimental results on a set of benchmarks show frequently 20% to 50% reduction in instruction cache misses. By better utilizing the shared cache, the new techniques magnify the throughput improvement of hyper-threading by 8%