News: I defended in August 2008, and am now
at Oracle Labs
Research
Interests
My current research is in concurrency (algorithms, transactional
memory, semantics, runtime systems, programming models, languages,
compiler and architectural support).
My (outdated) CV
Publications
Prior
-
"A Comprehensive Contention Management Strategy for Software
Transactional Memory", by Michael F. Spear, Luke Dalessandro,
Virendra J. Marathe, and Michael L. Scott. In the
14th ACM Symposium on
Principles and Practice of Parallel Programming (PPoPP'09),
February 2009.
-
"Ordering-Based Semantics for Software Transactional Memory",
by Michael F. Spear, Luke Dalessandro, Virendra J. Marathe,
and Michael L. Scott. In the
12th International Conference on Principles of Distributed
Systems (OPODIS'08), December 2008.
-
"Scalable Techniques for
Transparent Privatization in Software Transactional Memory", by
Virendra J. Marathe, Michael F. Spear, and Micheal L. Scott. In
the 37th
International Conference on Parallel Processing (ICPP'08),
September 2008.
-
"Toward High Performance
Nonblocking Software Transactional Memory", by Virendra
J. Marathe, and Mark Moir. In
the 13th ACM SIGPLAN
Symposium on Principles and Practice of Parallel Programming
(PPoPP'08), February 2008.
-
"Transaction Safe
Nonblocking Data Structures", by Virendra J. Marathe, Michael
F. Spear, and Michael L. Scott. In
the 21st International
Symposium on Distributed Computing (DISC'07) (brief announcements
track), September 2007.
-
"Delaunay Triangulation
with Transactions and Barriers", by Michael L. Scott, Michael
F. Spear, Luke Dalessandro, and Virendra J. Marathe. In
the IEEE
International Symposium on Workload Characterization (IISWC'07)
(benchmarks track), September 2007.
-
"Capabilities and
Limitations of Library-Based Software Transactional Memory in
C++", by Luke Dalessandro, Virendra J. Marathe, Michael F. Spear,
and Michael L. Scott. In
the 2nd
ACM SIGPLAN Workshop on Transactional Computing (TRANSACT'07),
August 2007.
- "
Privatization Techniques for Software Transactional Memory", by
Michael F. Spear, Virendra J. Marathe, Luke Dalessandro, and Michael
L. Scott. In Proceedings of the 26th ACM Symposium on Principles
of Distributed Computing (PODC'07) (brief announcement track),
August 2007.
- "Transactions and
Privatization in Delaunay Triangulation", by Michael L. Scott,
Michael F. Spear, Luke Dalessandro, and Virendra J. Marathe. In
Proceedings of the 26th ACM
Symposium on Principles of Distributed Computing (PODC'07) (brief
announcement track), August 2007.
- "An Integrated
Hardware-Software Approach to Flexible Transactional Memory", by
Arrvindh Shriraman, Michael F. Spear, Hemayat Hossain, Virendra
J. Marathe, Sandhya Dwarkadas, and Michael L. Scott. In Proceedings
of the 34th International
Symposium on Computer Architecture (ISCA'07), June 2007.
- "Featherweight
Transactions: Decoupling Threads and Atomic Blocks", by Virendra
J. Marathe, Tim Harris, and James R. Larus. In Proceedings of the
ACM SIGPLAN Symposium on Principles and
Practice of Parallel Programming (PPoPP'07) (poster paper),
March 2007.
- "Efficient
Nonblocking Software Transactional Memory", by Virendra
J. Marathe, and Mark Moir. In Proceedings of the ACM SIGPLAN Symposium on Principles and
Practice of Parallel Programming (PPoPP'07) (poster paper),
March 2007.
- "Conflict Detection and
Validation Strategies for Software Transactional Memory", by
Michael F. Spear, Virendra J. Marathe, William N. Scherer III, and
Michael L. Scott. In Proceedings of the 20th International Symposium on
Distributed Computing (DISC'06), September 2006.
- "Lowering the
Overhead of Software Transactional Memory", by Virendra
J. Marathe, Michael F. Spear, Christopher Heriot, Athul Acharya, David
Eisenstat, William N. Scherer III, and Michael L. Scott. In
Proceedings of the 1st
ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for
Transactional Computing (Transact'06), June 2006.
- "Hardware
Acceleration of Software Transactional Memory", by Arrvindh
Shriraman, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott,
David Eisenstat, Christopher Heriot, William N. Scherer III, and
Michael F. Spear. In Proceedings of the 1st
ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for
Transactional Computing (Transact'06), June 2006.
- "Composite Abortable
Locks", by Virendra J. Marathe, Mark Moir, and Nir Shavit. In
Proceedings of the 20th IEEE
International Parallel and Distributed Processing Symposium
(IPDPS'06), April 2006.
- "Transaction
Synchronizers", by Victor Luchangco and Virendra J. Marathe. In
Proceedings of Workshop on Synchronization
and Concurrency in Object-Oriented Languages (SCOOL'05) held
in conjunction with the 20th Annual
Symposium on Object-Oriented Programming, Systems, Languages and
Applications (OOPSLA'05), October 2005.
- "Adaptive Software
Transactional Memory", by Virendra J. Marathe, William N. Scherer
III, and Michael L. Scott. In Proceedings of the 19th
International Symposium on Distributed Computing (DISC'05),
September 2005.
- "Using LL/SC to Simplify
Word-based Software Transactional Memory", by Virendra J. Marathe
and Michael L. Scott. In the 24th Annual Symposium on
Principles of Distributed Computing (PODC'05) (poster paper),
July 2005.
- "Design Tradeoffs in
Modern Software Transactional Memory Systems", by Virendra
J. Marathe, William N. Scherer III, and Michael L. Scott. In
Proceedings of the 7th
Workshop on Languages, Compilers, and Run-time Support for Scalable
Systems (LCR'04), October 2004.
- "The Design of an
Interval Routing Enabled Publish/Subscribe Communications Protocol for
Ad Hoc Sensor Networks", by Virendra J. Marathe, and Ted
Herman. In Proceedings of the Fall 2002 Midwest Society of
Programming Languages and Systems Workshop (MSPLS'02), November
2002.
Technical Reports and Other Manuscripts
-
"Enhancing the Peformance
and Usability of Software Transactional Memory",
Ph.D. Thesis, August 2008.
-
"Efficient Nonblocking
Software Transactional Memory", by Virendra J. Marathe, and Mark
Moir. TR 932, Department of Computer Science, University of
Rochester, March 2008.
-
"Transaction Safe
Nonblocking Data Structures", by Virendra J. Marathe, and Michael
L. Scott. TR 924, Department of Computer Science, University of
Rochester, September 2007.
-
"Privatization
Techniques for Software Transactional Memory", by Michael
F. Spear, Virendra J. Marathe, Luke Dalessandro, and Michael
L. Scott. TR 915, Department of Computer Science, University of
Rochester, February 2007.
-
"Lowering the Overhead
of Software Transactional Memory", by Virendra J. Marathe, Michael
F. Spear, Christopher Heriot, Athul Acharya, David Eisenstat, William
N. Scherer III, and Michael L. Scott. TR 893, Department of
Computer Science, University of Rochester, March 2006.
-
"Hardware Acceleration
of Software Transactional Memory", by Arrvindh Shriraman, Virendra
J. Marathe, Sandhya Dwarkadas, Michael L. Scott, David Eisenstat,
Christopher Heriot, William N. Scherer III, and Michael
F. Spear. TR 887, Department of Computer Science, University of
Rochester, March 2006.
-
"Adaptive Software
Transactional Memory", by Virendra J. Marathe, William N. Scherer
III, and Michael L. Scott. TR 868, Department of Computer Science,
University of Rochester, May 2005.
-
"A Qualitative
Survey of Modern Software Transactional Memory Systems", by
Virendra J. Marathe, and Michael L. Scott. TR 839, Department of
Computer Science, University of Rochester, June 2004.
-
"An Interval Routing
enabled Publish/Subscribe Communications Protocol for Ad Hoc Sensor
Networks". Masters Thesis, accepted in August 2003 at The
University of Iowa.
Posters
-
"Featherweight
Transactions: Decoupling Threads and Atomic Blocks", by Virendra
J. Marathe, Tim Harris, and James
R. Larus. In ACM SIGPLAN Symposium
on Principles and Practice of Parallel Programming, March
2007.
-
"Efficient Nonblocking
Software Transactional Memory", by Virendra J. Marathe, and Mark
Moir. In ACM SIGPLAN Symposium on
Principles and Practice of Parallel Programming, March
2007.
-
"Using LL/SC to Simplify Word-based Software Transactional Memory", by
Virendra J. Marathe, and Michael
L. Scott. In 24th Annual
ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing,
Poster Track, July 2005.
Talks
-
Scalable Techniques for Transparent Privatization in Software
Transactional
Memory. In the
37th International Conference on Parallel Processing
(ICPP'08), September 2008
(pdf).
-
Guilt-free Nonblocking Software Transactional Memory. Invited
Talk. Sun Microsystems, Menlo Park, April 2008
(ppt).
-
Toward High Performance Nonblocking Software Transactional
Memory. In the 13th
ACM SIGPLAN Symposium on Principles and Practice of Parallel
Programming (PPoPP'08), February 2008
(ppt).
-
Transaction Safe Nonblocking Data
Structures. In the
21st International Synposium on Distributed Computing
(DISC'07), September 2007
(ppt).
-
Privatization Techniques for Software Transactional
Memory. In the 26th
Annual ACM SIGACT-SIGOPS Symposium on Principles of Distributed
Computing (PODC'07), August 2007
(ppt).
-
Composite Abortable Locks. In the
20th IEEE International Parallel and Distributed Processing Symposium
(IPDPS'06), April 2006
(ppt).
-
Transaction Synchronizers. In Workshop
on Synchronization
and Concurrency in Object-Oriented Languages (SCOOL'05),
October 2005 (ppt).
-
Adaptive Software Transactional
Memory. In 19th
International Symposium on Distributed Computing (DISC'05),
September 2005 (ppt).
-
Design Tradeoffs in Modern Software Transactional Memory
Systems. In 7th Workshop
on Languages, Compilers, and Run-time Support for Scalable Systems
(LCR'04), October 2004
(ppt).
-
The Design of an Interval Routing Enabled Publish/Subscribe
Communications Protocol for Ad Hoc Sensor Networks. In Fall 2002
Midwest Society of Programming Languages and Systems Workshop
(ppt)
Teaching Assistantships
- CSC 101: Computer Science without Programming. Fall 2004. Instructor: Mitsunori Ogihara.
- CSC 258/458: Advanced Systems. Spring 2005. Instructor: Sandhya Dwarkadas.
- CSC 255/455: Advanced Programming Systems. Fall 2005. Instructor: Chen Ding.
Contact Address
Virendra Jayant Marathe
Department of Computer Science
University of Rochester
160 Trustee Road
Rochester, NY-14627
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