Virendra J. Marathe

Ph.D. in Computer Science
Department of Computer Science
University of Rochester
Advisor: Prof. Michael L. Scott

Email:

News: I defended in August 2008, and am now at Oracle Labs

Research

Interests

My current research is in concurrency (algorithms, transactional memory, semantics, runtime systems, programming models, languages, compiler and architectural support).

My (outdated)
CV

Publications

Recent

Prior

  1. "A Comprehensive Contention Management Strategy for Software Transactional Memory", by Michael F. Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott. In the 14th ACM Symposium on Principles and Practice of Parallel Programming (PPoPP'09), February 2009.
  2. "Ordering-Based Semantics for Software Transactional Memory", by Michael F. Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott. In the 12th International Conference on Principles of Distributed Systems (OPODIS'08), December 2008.
  3. "Scalable Techniques for Transparent Privatization in Software Transactional Memory", by Virendra J. Marathe, Michael F. Spear, and Micheal L. Scott. In the 37th International Conference on Parallel Processing (ICPP'08), September 2008.
  4. "Toward High Performance Nonblocking Software Transactional Memory", by Virendra J. Marathe, and Mark Moir. In the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'08), February 2008.
  5. "Transaction Safe Nonblocking Data Structures", by Virendra J. Marathe, Michael F. Spear, and Michael L. Scott. In the 21st International Symposium on Distributed Computing (DISC'07) (brief announcements track), September 2007.
  6. "Delaunay Triangulation with Transactions and Barriers", by Michael L. Scott, Michael F. Spear, Luke Dalessandro, and Virendra J. Marathe. In the IEEE International Symposium on Workload Characterization (IISWC'07) (benchmarks track), September 2007.
  7. "Capabilities and Limitations of Library-Based Software Transactional Memory in C++", by Luke Dalessandro, Virendra J. Marathe, Michael F. Spear, and Michael L. Scott. In the 2nd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT'07), August 2007.
  8. " Privatization Techniques for Software Transactional Memory", by Michael F. Spear, Virendra J. Marathe, Luke Dalessandro, and Michael L. Scott. In Proceedings of the 26th ACM Symposium on Principles of Distributed Computing (PODC'07) (brief announcement track), August 2007.
  9. "Transactions and Privatization in Delaunay Triangulation", by Michael L. Scott, Michael F. Spear, Luke Dalessandro, and Virendra J. Marathe. In Proceedings of the 26th ACM Symposium on Principles of Distributed Computing (PODC'07) (brief announcement track), August 2007.
  10. "An Integrated Hardware-Software Approach to Flexible Transactional Memory", by Arrvindh Shriraman, Michael F. Spear, Hemayat Hossain, Virendra J. Marathe, Sandhya Dwarkadas, and Michael L. Scott. In Proceedings of the 34th International Symposium on Computer Architecture (ISCA'07), June 2007.
  11. "Featherweight Transactions: Decoupling Threads and Atomic Blocks", by Virendra J. Marathe, Tim Harris, and James R. Larus. In Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'07) (poster paper), March 2007.
  12. "Efficient Nonblocking Software Transactional Memory", by Virendra J. Marathe, and Mark Moir. In Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'07) (poster paper), March 2007.
  13. "Conflict Detection and Validation Strategies for Software Transactional Memory", by Michael F. Spear, Virendra J. Marathe, William N. Scherer III, and Michael L. Scott. In Proceedings of the 20th International Symposium on Distributed Computing (DISC'06), September 2006.
  14. "Lowering the Overhead of Software Transactional Memory", by Virendra J. Marathe, Michael F. Spear, Christopher Heriot, Athul Acharya, David Eisenstat, William N. Scherer III, and Michael L. Scott. In Proceedings of the 1st ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing (Transact'06), June 2006.
  15. "Hardware Acceleration of Software Transactional Memory", by Arrvindh Shriraman, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott, David Eisenstat, Christopher Heriot, William N. Scherer III, and Michael F. Spear. In Proceedings of the 1st ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing (Transact'06), June 2006.
  16. "Composite Abortable Locks", by Virendra J. Marathe, Mark Moir, and Nir Shavit. In Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS'06), April 2006.
  17. "Transaction Synchronizers", by Victor Luchangco and Virendra J. Marathe. In Proceedings of Workshop on Synchronization and Concurrency in Object-Oriented Languages (SCOOL'05) held in conjunction with the 20th Annual Symposium on Object-Oriented Programming, Systems, Languages and Applications (OOPSLA'05), October 2005.
  18. "Adaptive Software Transactional Memory", by Virendra J. Marathe, William N. Scherer III, and Michael L. Scott. In Proceedings of the 19th International Symposium on Distributed Computing (DISC'05), September 2005.
  19. "Using LL/SC to Simplify Word-based Software Transactional Memory", by Virendra J. Marathe and Michael L. Scott. In the 24th Annual Symposium on Principles of Distributed Computing (PODC'05) (poster paper), July 2005.
  20. "Design Tradeoffs in Modern Software Transactional Memory Systems", by Virendra J. Marathe, William N. Scherer III, and Michael L. Scott. In Proceedings of the 7th Workshop on Languages, Compilers, and Run-time Support for Scalable Systems (LCR'04), October 2004.
  21. "The Design of an Interval Routing Enabled Publish/Subscribe Communications Protocol for Ad Hoc Sensor Networks", by Virendra J. Marathe, and Ted Herman. In Proceedings of the Fall 2002 Midwest Society of Programming Languages and Systems Workshop (MSPLS'02), November 2002.

Technical Reports and Other Manuscripts

  1. "Enhancing the Peformance and Usability of Software Transactional Memory", Ph.D. Thesis, August 2008.
  2. "Efficient Nonblocking Software Transactional Memory", by Virendra J. Marathe, and Mark Moir. TR 932, Department of Computer Science, University of Rochester, March 2008.
  3. "Transaction Safe Nonblocking Data Structures", by Virendra J. Marathe, and Michael L. Scott. TR 924, Department of Computer Science, University of Rochester, September 2007.
  4. "Privatization Techniques for Software Transactional Memory", by Michael F. Spear, Virendra J. Marathe, Luke Dalessandro, and Michael L. Scott. TR 915, Department of Computer Science, University of Rochester, February 2007.
  5. "Lowering the Overhead of Software Transactional Memory", by Virendra J. Marathe, Michael F. Spear, Christopher Heriot, Athul Acharya, David Eisenstat, William N. Scherer III, and Michael L. Scott. TR 893, Department of Computer Science, University of Rochester, March 2006.
  6. "Hardware Acceleration of Software Transactional Memory", by Arrvindh Shriraman, Virendra J. Marathe, Sandhya Dwarkadas, Michael L. Scott, David Eisenstat, Christopher Heriot, William N. Scherer III, and Michael F. Spear. TR 887, Department of Computer Science, University of Rochester, March 2006.
  7. "Adaptive Software Transactional Memory", by Virendra J. Marathe, William N. Scherer III, and Michael L. Scott. TR 868, Department of Computer Science, University of Rochester, May 2005.
  8. "A Qualitative Survey of Modern Software Transactional Memory Systems", by Virendra J. Marathe, and Michael L. Scott. TR 839, Department of Computer Science, University of Rochester, June 2004.
  9. "An Interval Routing enabled Publish/Subscribe Communications Protocol for Ad Hoc Sensor Networks". Masters Thesis, accepted in August 2003 at The University of Iowa.

Posters

  1. "Featherweight Transactions: Decoupling Threads and Atomic Blocks", by Virendra J. Marathe, Tim Harris, and James R. Larus. In ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, March 2007.
  2. "Efficient Nonblocking Software Transactional Memory", by Virendra J. Marathe, and Mark Moir. In ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, March 2007.
  3. "Using LL/SC to Simplify Word-based Software Transactional Memory", by Virendra J. Marathe, and Michael L. Scott. In 24th Annual ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing, Poster Track, July 2005.

Talks

  1. Scalable Techniques for Transparent Privatization in Software Transactional Memory. In the 37th International Conference on Parallel Processing (ICPP'08), September 2008 (pdf).
  2. Guilt-free Nonblocking Software Transactional Memory. Invited Talk. Sun Microsystems, Menlo Park, April 2008 (ppt).
  3. Toward High Performance Nonblocking Software Transactional Memory. In the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'08), February 2008 (ppt).
  4. Transaction Safe Nonblocking Data Structures. In the 21st International Synposium on Distributed Computing (DISC'07), September 2007 (ppt).
  5. Privatization Techniques for Software Transactional Memory. In the 26th Annual ACM SIGACT-SIGOPS Symposium on Principles of Distributed Computing (PODC'07), August 2007 (ppt).
  6. Composite Abortable Locks. In the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS'06), April 2006 (ppt).
  7. Transaction Synchronizers. In Workshop on Synchronization and Concurrency in Object-Oriented Languages (SCOOL'05), October 2005 (ppt).
  8. Adaptive Software Transactional Memory. In 19th International Symposium on Distributed Computing (DISC'05), September 2005 (ppt).
  9. Design Tradeoffs in Modern Software Transactional Memory Systems. In 7th Workshop on Languages, Compilers, and Run-time Support for Scalable Systems (LCR'04), October 2004 (ppt).
  10. The Design of an Interval Routing Enabled Publish/Subscribe Communications Protocol for Ad Hoc Sensor Networks. In Fall 2002 Midwest Society of Programming Languages and Systems Workshop (ppt)

Teaching Assistantships

  1. CSC 101: Computer Science without Programming. Fall 2004. Instructor: Mitsunori Ogihara.
  2. CSC 258/458: Advanced Systems. Spring 2005. Instructor: Sandhya Dwarkadas.
  3. CSC 255/455: Advanced Programming Systems. Fall 2005. Instructor: Chen Ding.

Contact Address

Virendra Jayant Marathe
Department of Computer Science
University of Rochester
160 Trustee Road
Rochester, NY-14627