Consensus limitation last time: 2. Synchronous settings: Need f+1 rounds, even if all f faults are crashes. For Byzantine faults, need also n > 3f. Questions? ------------------------ This time: 1. (Most) asynchronous settings: Entirely impossible, even with just one crash. Also, maybe: Sketch of Aguilera-Toueg alternative approach for last time, based (also) on prolonging ``bivalence.'' ------------------------ Recall reduction last time: Synchronous (3,1) protocol *using* (6,2) protocol. (Latter straightforwardly generalizes to *any* (n,f) with n <= 3f .) (Unsatisfying aspect of this elegance: No obvious direct intuition *why* (6,2) is impossible. Suggestions? Similar issue below.) In the same spirit, this time: Asynchronous (2,1) R/W protocol *using* any such (n,1). (Wlog (Chapter 10): No shared writing.) (Then need just show (2,1) is impossible.) The novelty: No static or full delegation to either simulating processor. Instead, perform a *collaborative*, *joint* simulation of the whole n-processor system (adopting its consensus). Each next step (or assignment of input) depends on which simulating processor ``happens to get there first'' (for which we will need some simple sort of mutual exclusion). (Differences from the usual mutual exclusion: no one ever exits, one may crash.) (The input to each simulated processor will thus be the input imposed by one of the simulating processors.) (Interesting case: What if one of the processors is fast enough to do *all* of the imposing, but then crashes? The consensus will then be his value, even if it is different from that of the one survivor! Note that this does not violate the definition of validity that we are using (p. 103). Does it make sense also to study a version of validity that insists on agreement with a unanimous initial opinion of ultimate survivors?) Therefore any crash by just one of the two can tie up the simulation of only one simulated processor, with the other subsequently always ``getting to the others first.'' Following his own intended schedule (round robin is fine), each simulating processor will suggest the local result (including owned shared variables) of a next step for the indicated processor, based on straightforward collection of the relevant (shared) data: Each simulating processor can write to two shared registers for each step of each simulated processor: a suggested-next-local-state register (initially null), and a victory flag (initially null). How to ``grab'': Write down suggestion based on your view. When subsequently to declare victory: No suggestion by competitor to declare tentative defeat: Otherwise How to interpret who won (i.e., which suggestion is law): declared victory (clear victory), or smaller uid if both declared tentative defeat (apparent ``tie'') (Lemma: Exactly one winner, unless one still there ``covering'' victory flag.) The rest (programming and proof) relatively routine? ------------------------ Why is (2,1) R/W protocol impossible? Suppose o.w. Initial configuration (0,0) ``0-valent'' (by validity) Initial configuration (1,1) ``1-valent'' (by validity) Show initial configuration (0,1) ``bivalent'' Proof: Make use of the univalences above. To get 0, initially crash second processor. to get 1, initially crash first processor. Show every bivalent configuration has a bivalent successor Proof: Suppose not. Wlog, say turn by first processor leads to 0-valence, and turn by second leads to 1-valence. If the turns ``commute'' then we have bivalence for both. Only noncommuting case: Read and write involving same register. But compare write, followed by crash of reader, with read, followed by the write, followed by crash of the reader --get both valences! Conclusion: Infinite bivalent execution, contradicting termination! ------------------------ What about the other asynchronous model, message passing? Simulation again: Could use protocol there to get R/W protocol. How? Use a shared register for each message buffer.