Emerging Memory Technologies

Charge-based memory technologies such as DRAM or NAND Flash are facing severe scalability problems due to precise charge placement and sensing hurdles in deep-submicron processes. In response, the industry is turning its attention to resistive memory technologies such as phase-change memory (PCM), memristors (RRAM), and spin-torque transfer magnetoresistive RAM (STT-MRAM)—memory technologies that rely on resistivity rather than charge as the information carrier, and thus hold the potential to scale to much smaller geometries than charge memories. Unlike the case of SRAM or DRAM, resistive memories rely on non-volatile, resistive information storage in a cell, and thus exhibit near-zero leakage in the data array. To exploit the benefits of resistive memories, however, resistive memories must first be architected to address relatively long latencies, high energy writes, and finite endurance.

Energy-Efficient Microprocessors using STT-MRAM

As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall.

In [ISCA’11], we explore resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STTMRAM)—a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage resistant, scalable RAM blocks and lookup tables, and by carefully rearchitecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7x and leakage power by 2.1x at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.

Phase-Change Memory as a Scalable DRAM Alternative 

Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM’s scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.

In [ISCA'09], we propose area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. The proposed memory architecture lays the foundation for exploiting PCM scalability and non-volatility in main memory. PCM scalability implies lower main memory energy and greater write endurance. Furthermore, non-volatile main memories hold the potential to fundamentally change the landscape of computing. Software cognizant of this newly provided persistence can provide qualitatively new capabilities. For example, system boot/hibernate can be perceived as instantaneous; application checkpointing can be made inexpensive; file systems can provide stronger safety guarantees. Thus, the analysis in this work is a step towards a fundamentally new memory hierarchy with deep implications across the hardware-software interface.

Better I/O via Byte-Addressable, Persistent Memory

For decades, computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new persistent, byte-addressable memory technologies such as PCM offer fast, fine-grained access to persistent storage. Whereas existing systems must compromise between the speed of volatile memory and the safety of non-volatile storage, systems based on persistent, byte-addressable memory can provide the best of both worlds.

In [SOSP'09], we present a file system and a hardware architecture that are built around the properties of persistent, byte-addressable memory. Our file system, PFS, uses atomic, fine-grained updates to persistent storage in order to provide better performance and stronger safety and consistency guarantees than traditional file systems, even when compared on the same memory technologies. Our hardware architecture enforces the atomicity and ordering guarantees required by PFS while still providing the benefits of the L1 and L2 caches. On top of stronger safety and consistency guarantees, the superior performance of this storage system effectively eliminates the need to block and context-switch an application during file I/O.

Building Reliable Systems from Nanoscale Resistive Memories

DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a promising DRAM replacement. Unfortunately, PCM is write-limited, and current approaches to managing writes must decommission pages of PCM when the first bit fails.


In [ASPLOS'10], we present dynamically replicated memory (DRM), the first hardware and operating system interface designed for PCM that allows continued operation through graceful degradation when hard faults occur. DRM reuses memory pages that contain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage. No changes are required to the processor cores, the cache hierarchy, or the operating system’s page tables. By changing the memory controller, the TLBs, and the operating system to be DRM-aware, we can improve the lifetime of PCM by up to 40x over conventional error-detection techniques.