Monday, September 24, 2007
Computer Science Bldg. Room 209
Dr. Rajeev Balasubramonian
University of Utah
Architecting Efficient Interconnects for Large Caches
Future multi-core chips will allocate a large fraction of chip
area to support multi-megabyte cache hierarchies. Complex
on-chip networks will be required to connect the many cores
and cache banks in such a chip. The on-chip network plays a
significant role in determining overall processor performance
and power. The talk will first describe the creation of a tool
(CACTI 6.0) that carefully considers on-chip network parameters
in estimating an optimal cache organization. It will then
discuss novel mechanisms to improve the performance and power
of the on-chip network.
Rajeev Balasubramonian received his B.Tech in Computer Science
and Engineering from the Indian Institute of Technology, Bombay
in 1998. He received his MS (2000) and Ph.D. (2003) degrees
from the University of Rochester. He joined the faculty at
the School of Computing, University of Utah in August 2003.
His primary research areas include memory hierarchies,
on-chip interconnects, reliability, and 3D die stacking.
Dr. Balasubramonian is a recipient of the NSF CAREER award and
multiple teaching awards from the University of Utah. As a
graduate student, he received the IBM Ph.D. Fellowship and
the University of Rochester Sproull Fellowship.
Refreshments provided at 10:45