Tuesday, April 08, 2014
9:30 AM
Xian-He Sun
Illinois Institute of Technology
The Design of Parallel Memory Systems
Computing becomes more and more data-intensive. Newly emerged data-intensive applications compounded with the lasting memory-wall problem makes data access the prominent performance bottleneck of high-end computing. The parallelism of multi-core processors puts even more pressure on the already lagging memory systems. A natural way to improve memory performance is to increase and utilize memory concurrency. We argue that substantial memory concurrency exists at each layer of current memory systems, but it has not been fully utilized. Historically, memory concurrency is designed and utilized around computing. A paradigm shift is needed to support sustained data accessing from a data-centric view. In this talk we introduce the concept of parallel memory system. In an ideal parallel memory system, the system will explicitly express and utilize parallel data accesses. This awareness is largely missing from current memory systems. First, we review the concurrency available in modern memory systems, and propose the C-AMAT formulation for system design analysis of concurrent data accesses. Next, we illustrate the difference between the memory concurrency from a computing-centric view and the parallel memory from a data-centric view, and discuss the considerations of utilizing parallel data access for big data applications. Finally, we present some of our recent results which quantize and utilize parallel I/O following the parallel memory concept.

BI:Dr. Xian-He Sun is a Distinguished Professor of Computer Science and the chairman of the Department of Computer Science at the Illinois Institute of Technology (IIT). He is the director of the Scalable Computing Software laboratory at IIT and a guest faculty in the Mathematics and Computer Science Division at the Argonne National Laboratory. Before joining IIT, he worked at DoE Ames National Laboratory, at ICASE, NASA Langley Research Center, at Louisiana State University, Baton Rouge, and was an ASEE fellow at Navy Research Laboratories. Dr. Sun is an IEEE fellow and is known for his memory-bounded speedup model, also called Sun-Niís Law, for scalable computing. His research interests include parallel and distributed processing, high-end computing, memory and I/O systems, and performance evaluation. He has close to 200 publications and 4 patents in these areas. He is a former IEEE CS distinguished speaker and former vice chair of the IEEE Technical Committee on Scalable Computing, and is serving and served on the editorial board of most of the leading professional journals in the field of parallel processing. More information about Dr. Sun can be found at his web site www.cs.iit.edu/~sun/.