Abstract: Heterogeneous systems that couple CPUs withrammable Gate Array In this talk, I will first present the on-chip storage and multitasking optimization techniques for GPUs. The proposed techniques leverage on compile-time and run-time techniques to improve the cache performance, register utilization, pipeline utilization and overall performance. For the second half of the talk, I will present performance modeling and optimization techniques for FPGAs based on OpenCL programming model.
Bio: Yun (Eric) Liang is currently an assistant professor in School of EECS at Peking University, China. Before joining Peking University, he was a Research Scientist in University of Illinois at Champaign Urbana. He received the B.S degree from Tongji University, Shanghai, and the Ph.D degree in computer science from National University Singapore. He has published more than 40 research papers in the top conferences and journals on compilation, computer architecture, and embedded system including MICRO, HPCA, ISCA, DAC, CGO, ICCAD, FPGA, FCCM, etc. His work has received the Best Paper Award of FCCM 2011 and Best Paper Award nominations from ASPDAC 2016, DAC 2012, FPT 2011, and CODES+ISSS 2008.