As the benefits from transistor scaling slow down, specialized accelerators and heterogeneous computing are becoming increasingly important because they can significantly improve performance and energy efficiency for specific applications. An efficient and easy-to-program memory and communication architecture is critical in achieving the promise of such systems. Traditionally, accelerators in heterogeneous systems used discrete address spaces and employed specialized memories, e.g., scratchpads, for specific access patterns. These attributes make these systems difficult to program and inefficient in the presence of high data reuse and fine-grained synchronization -- traits that are common in emerging applications such as graph analytics workloads. My thesis resolves these inefficiencies with cross-cutting research that rethinks the software, hardware, and hardware-software interface of heterogeneous systems. Underlying my work is the efficient support of a global address space across all accelerator memories (for easier programming), an efficient cache coherence protocol (for efficient hardware), and a familiar memory consistency model (for an appropriate hardware-software interface).
First, I consider heterogeneous systems that have recently started to support global address spaces. I expose the imbalance between coherence and consistency in such systems. Current systems use simple, software-based coherence protocols that require heavyweight actions at synchronization points. To deal with this, industry has moved to complex consistency models that use scoped synchronization, making consistency models for heterogeneous systems even more complex than the already complicated CPU consistency models. I introduce a low overhead cache coherence protocol, DeNovo, that adjusts the imbalance and enables heterogeneous systems to use the standard, simpler data-race-free (DRF) consistency model. Second, I explore a further source of complexity in consistency models: relaxed atomics. These have been the Achilles heel of CPU consistency models -- they have the promise of higher performance but have no known formal semantics. Heterogeneous systems' inefficient support for atomics makes using relaxed atomics particularly tempting. I extend the DRF consistency model to retain the efficiency benefits of relaxed atomics and provide better semantics for the common use cases of relaxed atomics in heterogeneous systems. Third, current systems continue to support specialized memories in private address spaces, which negate some of the benefits of specialization. I integrate these specialized memories into the global address space while retaining the benefits they provide. Overall, my research introduces a more efficient and easier-to-program heterogeneous memory hierarchy that significantly improves both performance and energy compared to the state-of-the-art heterogeneous systems.
Matt Sinclair is a doctoral candidate in the Department of Computer Science at the University of Illinois at Urbana-Champaign. He is interested in computer architecture and systems, with a current focus on building efficient memory hierarchies for heterogeneous systems. His papers at the 2015 International Symposium on Computer Architecture (ISCA) and 2015 International Symposium on Microarchitecture (MICRO) were recognized as 2016 IEEE Micro Top Picks Honorable Mentions. He is the recipient of a Qualcomm Innovation Fellowship, two Mavis Future Faculty Fellowships, the Feng Chen Memorial Award, the W.J. Poppelbaum Award, and a Saburo Muroga Fellowship. He was also selected to attend and present his research at the 2016 Heidelberg Laureate Forum. He received a BS in Computer Science with Honors & Computer Engineering (2009) and a MS in Electrical Engineering (2011) from the University of Wisconsin-Madison.