Joseph (Joe) Izraelevitz
(download CV as a pdf)
In the near future, DRAM is likely to be augmented or replaced by a variety of new main memory technologies, all of which share an interesting property: they are nonvolatile (their contents survive power outages). This nonvolatility raises intriguing possibilities for fault tolerance and for displacement of traditional I/O. My dissertation research lies at the intersection of Nonvolatile Memory Technologies and Parallel Programming. Specifically, I build both theoretical and practical infrastructure to give application programmers safe, high-performance, and reliable access to coming nonvolatile memory. This area is still in its infancy, but is rapidly growing in relevance as the technology becomes commercially available. In the future, I plan to work to integrate nonvolatile memory into the full system stack, exploring topics in operating systems, crash consistency, and compilers. More broadly, I plan to further leverage my knowledge and experience to explore intermittently powered devices, such as those expected in the Internet of Things.
Ph.D. in Computer Science - University of Rochester, Rochester, NY
Degree conferral: March 2018
Dissertation title: Concurrency Implications of Nonvolatile Byte-Addressable Memory
Advisor: Prof. Michael L. Scott, Dept. of Computer Science
B.S./M.S. in Computer Science - Washington University in St. Louis
Second major in History
Thesis title: Automated Archaeological Survey of Ancient Irrigation Canals
Advisor: Prof. Robert Pless, Dept. of Computer Science
- Sep 2018-Present
UCSD, San Diego, CA
Advisor: Prof. Steven Swanson
- Nonvolatile Systems The Nonvolatile Systems Lab at UCSD is a research group investigating the impact of new nonvolatile memory on the design of computer systems. Various projects exploring file systems, data structures, and transactional systems are underway.
- Jan 2018-Aug 2018
IMDEA Software, Madrid, Spain
Advisor: Dr. Alexey Gotsman
- Consensus protocols over RDMA In contrast to event based network protocols, RDMA allows us to directly access the memory of a remote machine, bypassing the remote CPU. These different and faster semantics give us the ability to rethink how traditional consensus protocols can be built. This project investigated how to leverage RDMA primitives in order to build extremely fast and provably correct consensus algorithms in the style of Paxos or Zookeeper’s ZAB.
University of Rochester, Computer Science Department, Rochester, NY
Advisor: Prof. Michael L. Scott
Infrastructure for Nonvolatile Memory
The replacement of DRAM with nonvolatile memory technologies (NVM) promises to create a new opportunity for fast, durable storage. However, at least in the near future, caches and registers are expected to remain volatile, meaning that their contents will be lost in the event of a crash. Consequently, programmers must carefully reason about the state of NVM in order to ensure that persistent data is consistent after a crash. In this line of work, I have built practical and theoretical techniques to allow application programmers to use and reason about NVM. In particular, I have proposed extremely relaxed semantic models that map easily onto all existing proposals, developed a composable correctness condition called durable linearizability, and proved that a simple transform exists to take any linearizable nonblocking data structure and create a durably linearizable analog that stores its state in NVM. On the practical side, I have built new data structures that meet the new correctness condition, created a method to compose durable transactions on these data structures, and built failure atomicity systems for crash-consistent updates.
Shared Memory Synchronization
In large shared-memory machines, synchronization and communication between threads is often a major obstacle to scalability. In order to improve the run-time performance of parallel programs, I investigated and designed synchronization primitives and concurrent data structures, with a particular focus on nonblocking algorithms. This work produced new nonblocking concurrent data structures along with hardware primitives to improve the performance of locks and barriers.
- June 2015-Aug 2016
Hewlett-Packard (HP) Labs, Palo Alto, CA
Research Associate, Systems Group,
Mentor: Dr. Terence Kelly
- Nonvolatile Memory and Persistent Caches
This work studied the implications that using NVM caches, in addition to NVM main memory, would have on system design (registers were assumed to remain transient). For this project, I built a high-performance failure atomicity system for high transaction volume and high concurrency. This internship resulted in three patent applications related to system infrastructure for persistent caches.
- Nonvolatile Memory and Persistent Caches
- June 2014-Sep 2014
Oracle Labs, Burlington, MA
Research Intern, Scalable Synchronization Group,
Mentors: Dr. Yossi Lev, Dr. Virendra Marathe
- Side-effects of Lock Elision This project investigated the performance eﬀects of lock elision using both optimistic software synchronization techniques and hardware transactional memory on real-world benchmarks. The lessons learned from this project were later used to develop new hardware primitives to accelerate locks and barriers.
- May 2009-Aug 2012
United States Army, Fort Carson, CO
- My three year service in the United States Army included one year-long deployment to Afghanistan as a staff officer. During my service, I filled positions in the battalion communications and planning groups, as well serving as a Tank Platoon Leader. While deployed, I served as the Battalion Afghan National Security Forces Liaison Oﬃcer, coordinating American logistical and training support for partnered security forces in Kandahar City.
I have published in top-tier venues including full papers in MICRO, ASPLOS, DISC×2, PACT, ACM TOPC, PPoPP, and ICPP, and short or workshop papers at SPAAx2, PODC, TRANSACTx2 and NVMWx2. My work in industrial labs has resulted in four patent applications.
Conference and Journal Publications
- Qingrui Liu, Joseph Izraelevitz, Se Kwon Lee, Michael L. Scott, Sam H. Noh, and Changhee Jung. iDO: Compiler-Directed Failure Atomicity for Nonvolatile Memory, In: 51st IEEE/ACM International Symposium on Microarchitecture (MICRO ‘18). Fukuoka, Japan. (to appear)
- Hensen Wen, Joseph Izraelevitz, Wentao Cai, H. Alan Beadle, and Michael L. Scott. Interval based memory reclamation, 2018. In: 23rd ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming PPoPP ’18. Vienna, Austria. (link)
- Joseph Izraelevitz and Michael L. Scott. Generality and speed in nonblocking dual containers. In: ACM Trans. on Parallel Computing, 3(4):22:1–22:37, 2017. (link)
- Joseph Izraelevitz, Lingxiang Xiang, and Michael L. Scott. Performance improvement via always-abort HTM. In: 26th Intl. Conf. on Parallel Architectures and Compilation Techniques. PACT ’17. Portland, OR, USA, 2017. (link) (slides)
- Faisal Nawab, Joseph Izraelevitz, Terence Kelly, Charles B. Morrey, Dhruva Chakrabarti, and Michael L. Scott. Dalí: A periodically persistent hash map. In: 31st Intl. Symp. on Distributed Computing. DISC ’17. Vienna, Austria, 2017. (link) (slides)
- Matthew Graichen, Joseph Izraelevitz, and Michael L. Scott. An unbounded nonblocking double-ended queue. In: 45th Intl. Conf. on Parallel Processing. ICPP ’16. Philadelphia, PA, USA, 2016. (link)
- Joseph Izraelevitz, Terence Kelly, and Aasheesh Kolli. Failure-atomic persistent memory updates via JUSTDO logging. In: 21st Intl. Conf. on Architectural Support for Programming Languages and Operating Systems. ASPLOS XXI. Atlanta, GA, USA, 2016. (link)
- Joseph Izraelevitz, Hammurabi Mendes, and Michael L. Scott. Linearizability of persistent memory objects under a full-system-crash failure model. In: 30th Intl. Conf. on Distributed Computing. DISC ’16. Paris, France, 2016. (link) (slides)
Other Peer-reviewed Publications (Workshop papers, brief announcements, etc.)
- Faisal Nawab, Joseph Izraelevitz, Charles B. Morrey, Dhruva Chakrabarti, and Michael L. Scott. Dalí: A periodically persistent hash map. In: 9th Annual Non-Volatile Memories Wkshp. NVMW ’18. San Diego, CA, USA, 2018.
- Joseph Izraelevitz, Virendra Marathe, and Michael L. Scott. Poster presentation: Composing durable data structures. In: 8th Annual Non-Volatile Memories Wkshp. NVMW ’17. San Diego, CA, USA, 2017. (link) (poster)
- Joseph Izraelevitz, Lingxiang Xiang, and Michael L. Scott. Performance improvement via always-abort HTM. In: 12th ACM SIGPLAN Wkshp. on Transactional Computing. TRANSACT ’17. Austin, TX, USA, 2017. (link)
- Joseph Izraelevitz, Alex Kogan, and Yossi Lev. Implicit acceleration of critical sections via unsuccessful speculation. In: 11th ACM SIGPLAN Wkshp. on Transactional Computing. TRANSACT ’16. Barcelona, Spain, 2016. (link)
- Joseph Izraelevitz, Hammurabi Mendes, and Michael L. Scott. Brief announcement: Preserving happens-before in persistent memory. In: 28th ACM Symp. on Parallelism in Algorithms and Architectures. SPAA’16. Asilomar Beach, CA, USA, 2016. (link) (slides)
- Joseph Izraelevitz and Michael L. Scott. Brief announcement: A generic construction for nonblocking dual containers. In: 2014 ACM Symp. on Principles of Distributed Computing. PODC ’14. Paris, France, 2014. (link)
- Joseph Izraelevitz and Michael L. Scott. Brief announcement: Fast dual ring queues. In: 26th ACM Symp. on Parallelism in Algorithms and Architectures. SPAA ’14. Prague, Czech Republic, 2014. (link)
Patents and Patent Applications
- Virendra Marathe and Joseph Izraelevitz. Systems and methods for constructing composable persistent data structures. US Patent US10007581B2. Oracle International Corporation. US, 2018.
- Terence Kelly, Charles B. Morrey, Dhruva Chakrabarti, Aasheesh Kolli, Qiong Cai, Andrew C. Walton, and Joseph Izraelevitz. Register store. Patent application filed. Hewlett Packard Enterprise. US, 2016.
- Faisal Nawab, Joseph Izraelevitz, Terence Kelly, Charles B. Morrey, and Dhruva Chakrabarti. Memory system to access uncorrupted data. Patent application filed. Hewlett Packard Enterprise. US, 2016.
- Joseph Izraelevitz, Terence Kelly, Aasheesh Kolli, and Charles B. Morrey. Resuming execution in response to failure. Patent application filed (WO2017074451). Hewlett Packard Enterprise. US, 2015.
Unrefereed Publications (TRs, theses, etc.)
- Joseph Izraelevitz. Concurrency Implications of Nonvolatile Byte-Addressable Memory. Ph.D. Thesis. Department of Computer Science, Department of Computer Science, University of Rochester, 2018. (link)
- Joseph Izraelevitz, Hammurabi Mendes, and Michael L. Scott. Linearizability of persistent memory objects under a full-system-crash failure model. Technical report (TR 999). Department of Computer Science, University of Rochester, 2016. (link)
- Joseph Izraelevitz and Michael L. Scott. A generic construction for nonblocking dual containers. Technical report (TR 992). Department of Computer Science, University of Rochester, 2014. (link)
- Joseph Izraelevitz and Michael L. Scott. Fast dual ring queues. Technical report (TR 990). Department of Computer Science, University of Rochester, 2014. (link)
- Joseph Izraelevitz. Automated archaeological survey of ancient irrigation canals. Master’s Thesis. Department of Computer Science, Washington University in St. Louis, 2009. (link)
- Joseph Izraelevitz. Poster presentation: Analyzing software dependencies on supercomputers with REV. In: Los Alamos National Laboratory Student Symp. Los Alamos, NM, USA, 2007.
Manuscripts in Progress
- Joseph Izraelevitz, Wentao Cai, Hensen Wen, Terence Kelly, Hideaki Kimura, and Michael L. Scott. Polytree: A synchronization framework for building ordered maps. In preparation.
- Joseph Izraelevitz, Alexey Gotsman, and Gregory Chockler. Acuerdo: Fast atomic broadcast over RDMA. Under review at ASPLOS, 2019.
Undergraduate and junior graduate students at the Univ. of Rochester have the opportunity, as part of some seminar courses, to work on independent research projects with senior graduate students. Often, these projects turn into full-ﬂedged research collaborations that continue after the end of the class, generally with minimal faculty supervision. Through this arrangement, I have been the primary research mentor for three students.
- Wentao Cai, M.S. at Univ. of Rochester (2016-2017)
Project: A framework for building nonblocking trees (in progress).
- Hensen Wen, M.S. at Univ. of Rochester (2016-2017)
Project: Interval Based Memory Reclamation
This eight month project resulted in a full paper at the Symp. on Principles and Practice of Parallel Programming (PPoPP’18)
- Matthew Graichen, B.S. at Univ. of Rochester (2014-2016)
Project: Unbounded Obstruction-Free Deques
This year-long project resulted in a full paper at the Intl. Conf. on Parallel Programming (ICPP’16).
Teaching Assistant for two semesters of CS200 (Undergraduate Research Seminar).
This class exposes undergraduates to the process of doing research. During the class, the students, in groups, complete a couple of research projects on open problems in computer science. As a TA, I was responsible for guiding these groups as they chose their research problems and for mentoring them as they worked their way towards solutions. I also gave two lectures on my own research, and was responsible for the normal TA duties (grading, attendance, etc.).
Teaching Assistant for CS486 (Computational Complexity).
This class is an in-depth exploration of complexity theory at the graduate level and is a required course for Ph.D. students, who normally take it in their first year. As this class is often students’ first exposure to difficult ideas in theoretical computer science, the TA office hours were well attended. While the primary instructor was out, I gave a series of three full lectures on class material, covering the Chomsky Hierarchy, with its associated grammars and machines, and Rice’s Theorem. I was also responsible for the normal TA duties (grading, office hours, etc.).
Honors and awards
- Hopeman Fellowship (School of Engineering scholarship), 2013.
- Sproull Fellow (full-tuition award to Univ. of Rochester), 2012-2013.
- Induction into Tau Beta Pi – Engineering Honor Society, 2009.
- Induction into Phi Alpha Theta – History Honor Society, 2009.
- George C. Marshall Cadet Award (top military graduate at Washington Univ. in St. Louis), 2009.
- Alexander S. Langsdorf Fellow (full-tuition merit-based award to Washington Univ. in St. Louis), 2004-2009.
- National Merit finalist, 2003.
- Assisted in writing CCF-1717712 ($449,937): “Data Structures and Transactions for Emerging Nonvolatile Memory,” awarded an NSF Small Proposal Grant in 2017; based on my work done on NVM and concurrent data structures at the University of Rochester.
- Awarded travel grants to PACT’17, SPAA’16.
- External PC Member
- Intl. Symp. on Memory Management (ISMM), 2017.
- ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming (PPoPP), Artifact Evaluation Committee, 2017.
- Intl. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2016.
- Intl. Conf. on Distributed Computing (DISC), 2014.
- ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming (PPoPP), 2018.
- IEEE Trans. on Parallel and Distributed Systems (TPDS), 2016.
- ACM Symp. on Parallelism in Algorithms and Architectures (SPAA), 2016.
- Intl. Symp. on Computer Architecture (ISCA), 2016.
- ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming (PPoPP), 2016.
- Intl. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2016.
- Invited talk at VMWare Research: Linearizability of Persistent Memory Objects Under a Full-System-Crash Failure Model. Palo Alto, CA, August 2016.
- Presented papers at ASPLOS, DISCx2, PACT, SPAAx2, TRANSACT×2.