Clustered microarchitectures attempt to
partition a single processor by grouping subsets of the functional units
with a correspondingly smaller amount of state, thereby allowing a faster
clock within the partitition or cluster. Additional clusters can be added,
thereby increasing the resources available to extract more
instruction-level parallelism (ILP). However,
communication across clusters requires extra cycles and can degrade
performance. Simultaneous multithreading (SMT) allows
multiple threads to share the resources of a superscalar machine,
thereby dynamically exploiting both thread-level parallelism (TLP) and
ILP on a cycle-by-cycle basis.
A straightforward use of SMT in a clustered microarchitecture can, however,
result in excessive communication overhead due to instructions from a single
thread being spread over a large number of clusters.
The goal of this project is to design a dynamically tunable clustered
multithreaded architecture (DT-CMT) that leverages the utilization advantages
of SMT and the clock speed advantages of clustering
while at the same time maximizing the performance of each individual thread.