Dynamically Tunable Clustered Multithreaded Architectures


Clustered microarchitectures attempt to partition a single processor by grouping subsets of the functional units with a correspondingly smaller amount of state, thereby allowing a faster clock within the partitition or cluster. Additional clusters can be added, thereby increasing the resources available to extract more instruction-level parallelism (ILP). However, communication across clusters requires extra cycles and can degrade performance. Simultaneous multithreading (SMT) allows multiple threads to share the resources of a superscalar machine, thereby dynamically exploiting both thread-level parallelism (TLP) and ILP on a cycle-by-cycle basis. A straightforward use of SMT in a clustered microarchitecture can, however, result in excessive communication overhead due to instructions from a single thread being spread over a large number of clusters. The goal of this project is to design a dynamically tunable clustered multithreaded architecture (DT-CMT) that leverages the utilization advantages of SMT and the clock speed advantages of clustering while at the same time maximizing the performance of each individual thread.


Sandhya Dwarkadas, David H. Albonesi, Chen Ding, Rajeev Balasubramonian, Ali El-Moursy, Rajeev Garg, Xipeng Shen, and Yutao Zhong.


Architectural Analysis

  • Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors, R. Balasubramonian, S. Dwarkadas, and D. Albonesi, International Symposium on Computer Architecture , June 2003.

  • Front-End Policies for Improved Issue Efficiency in SMT Processors, A. El-Moursy and D.H. Albonesi, 9th International Symposium on High-Performance Computer Architecture, pp. 31-40, February 2003.
  • "Partitioning Multi-Threaded Processors with a Large Number of Threads", A. El-Moursy, R. Garg, D. H. Albonesi, and S. Dwarkadas, International Symposium on Performance Analysis of Systems and Software, March 2005.

  • ``Compatible Phase Co-Scheduling on a CMP of Multi-Threaded Processors'', A. El-Moursy, R. Garg, D. H. Albonesi, and S. Dwarkadas, International Parallel and Distributed Processing Symposium, April 2006.

    Program Analysis

  • ``Characterizing and Predicting Program Behavior and its Variability'', E. Duesterwald, C. Cascaval, and S. Dwarkadas, International Conference on Parallel Architectures and Compilation Techniques (PACT) , September 2003.

  • The Energy Impact of Aggressive Loop Fusion", YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, and David H. Albonesi, in Proceedings of International Conference on Parallel Architecture and Compilation Techniques (PACT), Antibes Juan-les-pins, France, October 2004.

  • "Locality Phase Prediction", Xipeng Shen, Yutao Zhong, and Chen Ding, in Proceedings of Eleventh International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XI) , Boston, MA, October 2004.
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