Chair, Department of Computer Science
Computer Systems and Engineering Group
Department of Electrical and Computer Engineering
University of Rochester
Rochester, NY 14627-0226
sandhya at cs rochester edu
Phone (585) 275-5647; FAX 273-4556
Sandhya Dwarkadas received the B.Tech. degree from the Indian Institute of Technology, Madras, India, in 1986, and the M.S. and Ph.D. degrees from Rice University in 1989 and 1993, respectively.
She joined the faculty in the Computer Science Department at the University of Rochester in September, 1996. Her research interests lie in the areas of parallel and distributed computing, computer architecture, and the interaction and interface between the compiler, runtime/operating system, and underlying architecture. She has conducted research in several areas, including software distributed shared memory, integrated compiler and runtime support for parallelism, simulation methodology, uniprocessor and multiprocessor architectures, parallel applications development, and performance evaluation.
Her group is currently designing and implementing two-level and three-level protocols for shared memory on clusters of multiprocessors. The Cashmere protocol suite is one such effort to provide efficient shared memory support in software using remote memory access networks. InterAct is a system for distributed shared state that provides support for interactive applications with possibly more relaxed consistency requirements. InterWeave represents a merger and extension of our previous Cashmere and InterAct projects, combining hardware coherence within small multiprocessors, Cashmere-style lazy release consistency within tightly coupled clusters, and InterAct-style version-based consistency for distributed shared segments.
Complexity-Adaptive Processors (CAPs) leverage technology trends to combine the high clock speed of custom CMOS microprocessors with an adaptive scheme that dynamically optimizes an application's execution time and energy consumption. This is accomplished by trading clock speed for the complexity (e.g., size) of key hardware structures. Such adaptation requires cooperation among the compiler, the runtime system, and the underlying architecture, and is a challenging problem. This project is continuing to investigate adaptive designs for on-chip regular structures, as well as the role that the compiler can play in conjunction with the runtime in controlling overall chip configuration for optimized performance and energy consumption. Sandhya is also exploring techniques to create dynamically tunable clustered multithreaded architectures, as well as techniques to utilize idle processor resources for speculative execution.
The ARCH project (Architecture, Runtime, and Compiler Integration for High-Performance Computing) aims to improve the ease-of-use and performance of parallel systems by combining state-of-the-art compiler technology with an enhanced run-time system that exploits architectural features. Software distributed shared memory (DSM) is chosen as the preferred run-time for a distributed memory environment. A shared memory model is generally considered to be easier to program and compile for since there is no explicit need to worry about data motion. The goal of this project is to develop a uniform, platform-independent programming model for compiling and executing parallel programs without compromising efficiency.
From 1992-1996, Sandhya was a research scientist in the Computer Science Department at Rice University. At Rice, she was involved in the design and implementation of TreadMarks, a software distributed shared memory system running on a network of workstations. She also worked with Alejandro Schaffer on FASTLINK, a project to provide fast sequential and parallel genetic linkage analysis software.
As a graduate student, she developed an efficient execution-driven technique for the simulation of shared-memory multiprocessors. This technique was implemented as part of the Rice Parallel Processing Testbed (RPPT). She used this tool to design and evaluate synchronization support, adaptive caching techniques, and the use of relaxed consistency models for a hierarchical bus-based shared-memory architecture. These results contributed to the design of the Willow multiprocessor architecture. This work also lead to a classification of memory consistency models that, in addition to unifying all existing models into a common framework, provides insight into the implications of these models with respect to access ordering.
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