Sharanyan Srikanthan, URCS Grad Student

PhD Student (3rd Year - Systems Group)
Department of Computer Science
Room 727, Computer Studies Building,
University of Rochester,
New York - 14627

Email: srikanth at

I work on enabling operating systems extend the best possible performance to emerging parallel and multiprogrammed workloads by leveraging the use of hardware performance counters and in-depth understanding the strengths and weaknesses of the underlying hardware architecture. My advisor is Prof.Sandhya Dwarakadas . Below is a brief summary of my career so far.

Profile Summary

I am Sharanyan Srikanthan and I pursued my undergradation in Electronics and Communication Engineering in National Institute of Technology, Allahabad, India. At the undergraduate level, I started working on hardware design with a couple of projects in VHDL and later moved on to the more specific field of computer architecture. I have worked on processor simulators, memory hierarchy designs and more recently on parallel and high performance computing. The work mostly comprised of various adapting compute intensive programs for real time application on GPGPUs. I am enthused by the problem of effectively build a good architecture and also in using it using with tailor made, highly optimized programs that interact closely with the underlying hardware and thus extract maximum performance from it. This problem become a bit more complex when using interconnects are involved between various compute nodes with non-uniform memory accesses.

Currently, I am working on intelligent scheduling solutions for modern day parallel workloads that have threads competiting for and sharing resources. The aim is to run the right threads together such that they minimize the reduction in performance due to resource contention but also minimize communication over shared data thereby maximizing performance.

I worked for two years before joining grad school for pursuing my doctorate in computer science. During this time, I was lucky to get the chance to work with the BrahMos Aerospace, one of the best missile weapon systems India has produced. I was working adapting intensive algorithms on an NVIDIA GPU/FPGA/PowerPC platform so that it could be deployed for real time use. The work was successful and involved restructuring algorithms, build an effective hardware architecture for different types of algorithms while being constrained by time, space and power. Partitioning workload and minimising communication between the various modules in the embedded system added another dimension to the problem.

Areas of Interest

Conference Papers:


This is a copy of the write up for the CS 400 course
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