Sharanyan Srikanthan, URCS Grad Student
PhD Student (3rd Year - Systems Group)
Department of Computer Science
Room 727, Computer Studies Building,
University of Rochester,
New York - 14627
Email: srikanth at cs.rochester.edu
I work on enabling operating systems extend the best possible performance to emerging parallel and multiprogrammed workloads by leveraging the use of hardware performance counters and in-depth understanding the strengths and weaknesses of the underlying hardware architecture. My advisor is
Prof.Sandhya Dwarakadas. Below is a brief summary of my career so far.
Profile SummaryI am Sharanyan Srikanthan and I pursued my undergradation in Electronics and Communication Engineering in National Institute of Technology, Allahabad, India. At the undergraduate level, I started working on hardware design with a couple of projects in VHDL and later moved on to the more specific field of computer architecture. I have worked on processor simulators, memory hierarchy designs and more recently on parallel and high performance computing. The work mostly comprised of various adapting compute intensive programs for real time application on GPGPUs. I am enthused by the problem of effectively build a good architecture and also in using it using with tailor made, highly optimized programs that interact closely with the underlying hardware and thus extract maximum performance from it. This problem become a bit more complex when using interconnects are involved between various compute nodes with non-uniform memory accesses.
Currently, I am working on intelligent scheduling solutions for modern day parallel workloads that have threads competiting for and sharing resources. The aim is to run the right threads together such that they minimize the reduction in performance due to resource contention but also minimize communication over shared data thereby maximizing performance.
I worked for two years before joining grad school for pursuing my doctorate in computer science. During this time, I was lucky to get the chance to work with the BrahMos Aerospace, one of the best missile weapon systems India has produced. I was working adapting intensive algorithms on an NVIDIA GPU/FPGA/PowerPC platform so that it could be deployed for real time use. The work was successful and involved restructuring algorithms, build an effective hardware architecture for different types of algorithms while being constrained by time, space and power. Partitioning workload and minimising communication between the various modules in the embedded system added another dimension to the problem.
Areas of Interest
- Computer Architecture
- Operating Systems
- High Performance Computing
Sharanyan Srikanthan, Sandhya Dwarkadas, and Kai Shen, "Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing", In Proc. of the USENIX Annual Technical Conference, Denver, CO, June 2016. PDF Version
Sharanyan Srikanthan, Sandhya Dwarkadas, and Kai Shen, "Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems", In Proc. of the USENIX Annual Technical Conference, Santa Clara, CA, July 2015. PDF Version Code
Sharanyan Srikanthan, Arvind Kumar, "An Optimized Checkpointing Based Learning Algorithm for Single Event Upsets", Proc. IEEE International Conference on Computer Software and Applications-2010, Seoul, 19-23 July 2010.
Gupta, S.; Sharanyan, S.; Mukherjee, A.;, "Performance analysis of Support Vector Machine as classifier for voiced and unvoiced speech," Proc. IEEE 2010 International Conference on Computer and Communication Technology (ICCCT) 2010, vol., no., pp.397-401, 17-19 Sept. 2010.
Srikanthan, S.; Krishnan, V.; Kumar, A.;, "Online accelerated implementation of the Fuzzy C-means algorithm with the use of the GPU platform," Proc. IEEE International Conference on Computer and Communication Technology (ICCCT), 2011, vol., no., pp.385-388, 15-17 Sept. 2011.
Srikanthan, S.; Kumar, A.; Krishnan, V.;, "Accelerating the Euclidean distance matrix computation using GPUs," Proc. IEEE International Conference on Electronics Computer Technology (ICECT), 2011, vol.4, no., pp.422-426, 8-10 April 2011.
Srikanthan, S.; Kumar, A.; Gupta, R.;, "Implementing the dynamic time warping algorithm in multithreaded environments for real time and unsupervised pattern discovery," Proc. IEEE International Conference on Computer and Communication Technology (ICCCT), vol., no., pp.394-398, 15-17 Sept. 2011.
June - August 2011 : Accelerated Image Formation of Synthetic Aperture Radar in CUDA using NVIDIA GPUs
Worked with Defence Institute of Advanced Technology, Advanced Missile Technology, BrahMos Aerospace, Pune. The project was on Real-time implementation of SAR image formation (range and azimuth compression) and the results obtained resulted in speeding up the algorithm by 30-fold and thereby feasible for real time deployment.
September 2011 : Interfacing of radar target data with the BrahMos missile system using MIL STD 1553B protocol, BrahMos Aerospace, Hyderabad.
Interfacing missile fire control system with active radar link for uploading target information to missile prior to launch.
July 2011 : Interfacing Global Positioning System, GPRS and Google Earth with a laptop for remote object tracking
May - July 2010 : Implementation of Segmented Dynamic Time Warping in CUDA
Worked with Prof. Govindarajan, Indian Institute of Science, Bangalore. Restructured algorithm for SIMD architecture of GPUs. Speedup of about 35 times achieved with NVIDIA Tesla C1060 over Xeon processors.
September - December 2010 : Acceleration of modified Fuzzy C-Means clustering algorithm in CUDA
Worked with Asst Prof. Arvind Kumar, National Institute of Technology, Allahabad. Fuzzy C-Means, K-Means and Euclidean Distance Matrix were restructured and adapted for real-time execution on GPUs. Reduced branches, more data parallelism, memory access in bursts were objectives for restructuring of algorithm. Algorithm was faster by 40-50 times over state of the dual quad core Xeon processors.
May - July 2009 : Improvement of software resilience to single event upsets and hard errors
Worked under Dr. Shankar Balachandran, IIT Madras. SEU effect on hardware and different instructions was analyzed. Based on analyzed, software was profiled for resilience to SEUs and a dynamic partitioning based checkpoint method was used to eliminate SEUs. Code was analyzed as various graphs (control and data) and integer linear programming was used for dynamic partitioning.
May - July 2009 : Study of performance cache hierarchy and implementation of level-3 cache in simplescalar, the Microarchitectural simulator
Worked with Prof. Ranjini Parthasarathy, Anna University, Madras. Studied the effects of cache and varied various aspects to see the variation in performance of a processor. As a part of this study, I implemented an additional level (3rd Level) of cache and the improvement it can offer.
September - December 2009 : A Hybrid Classifier with Linear Predictive Coding and Bayesian, with Bayesian for error classification” in MNNIT, Allahabad.
Analyzed performance of various classifiers to classify speech. Introduced a novel idea of an error classifier and achieved an improved classification accuracy of 4% from a previously achieved accuracy of 14%.
January - March 2009 : Pipelined Reduced Instruction Set Computer design on FPGA using Verilog
Worked under Asst Prof. Arvind Kumar, MNNIT, Allahabad. 5 stage deep pipelined processor with 32 basic instructions with control for hazard management and data forwarding.
June - December 2008 : Design of a DDR SDRAMController on FPGA using VHDL
Worked under Asst Prof. Arvind Kumar, MNNIT. Studied various hardware components and hardware design procedures. Implemented a basic DDR SDRAM controller on an FPGA using VHDL.
This is a copy of the write up for the CS 400 course