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Systems Research

Computer systems research at URCS spans a range of topics, including program analysis and compiler technology; parallel, distributed, and mobile computing; cluster-based server technology; low-power hardware and software; processor and memory architecture; concurrency and synchronization; programming environments; and programming language design.

The department's core faculty in systems consists of John Criswell, Chen DingSandhya DwarkadasEngin Ipek, Sreepathi Pai, Michael Scott, and Yuhao Zhu. In addition, Wendi Heinzelman, and Michael Huang of electrical and computer engineering have joint appointments in CS, and are active in department research.


John Criswell

John Criswell's research interests focus on computer security and automatic compiler transformations that can be used to enforce security policies on commodity software.  He joined the department in 2014 after completing his PhD at the University of Illinois at Urbana-Champaign.

Chen Ding

Chen Ding is the recipient of a DOE Early Career Principal Investigator award and an NSF CAREER award. He joined URCS in July, 2000, after receiving his PhD at Rice University. His research is in program analysis and optimization, including computational and mathematical models of locality and parallelism and automatic and suggestion-based techniques for locality optimization, memory management and program parallelization.  He is widely known for his work on reuse distance to formally characterize locality and optimize data movement in the memory hierarchy of modern computer systems.

Sandhya Dwarkadas

Sandhya Dwarkadas is the recipient of an NSF Postdoctoral Fellowship and an NSF CAREER award, and has done work in the areas of software distributed shared memory, parallel architecture, and performance evaluation. She co-led the Cashmere and InterWeave distributed sharing projects, and leads the ARCH (Architecture, Run-time, and Compiler integration for High-performance computing) project.

Sreepathi Pai

Sree is an experimental computer systems researcher interested in the performance of computer programs. To that end, he works in computer architecture, compilers and the implementation of programming languages.

Sree works on heterogeneous accelerator-based systems consisting of CPUs and GPUs. His most recent work has revolved around optimizing compilers for high-performance irregular/graph algorithms on GPUs. Sree is also developing performance models for graph algorithms on GPUs.

Michael Scott

Michael Scott is an ACM fellow, an IEEE fellow, and the recipient of the University’s Goergen and Riker Teaching Awards, the Hajim School lifetime achievement award, and the 2006 Dijkstra Prize in Distributed Computing. He is widely known for his work on concurrent data structures and synchronization algorithms. He co-led the Cashmere and InterWeave distributed sharing projects. His textbook on programming language design and implementation (Programming Language Pragmatics, Morgan Kaufmann, fourth edition, 2016) is a leading reference in the field, with adoptions at over 200 schools. His text on Shared Memory Synchronization was published by Morgan & Claypool in 2013.

Yuhao Zhu

Yuhao Zhu's research interests are computer architecture and software design to enable future mobile systems that are energy-efficient, intelligent, and offer desirable Quality-of-Experience. To that end, his recent work specifically focuses on domain-specific systems for visual computing (e.g., imaging, AR/VR, computer vision) and Web technologies.

Prior to join University of Rochester, he was a Visiting Researcher at ARM Research and a Research Fellow at Harvard University. He received his Ph.D. from UT Austin while being supported by the Google Ph.D. Fellowship.

Wendi Heinzelman

Wendi Heinzelman is the recipient of an NSF CAREER award, an ONR Young Investigator award, and the University’s Curtis Teaching Award. She came to Rochester in January 2001, after receiving her PhD from MIT. Her research involves algorithms and protocols for wireless sensor networks and wireless video delivery. She leads the Wireless Communications and Networking group.

Michael Huang

Michael Huang joined the faculty in September 2002, after receiving his PhD from the University of Illinois at Urbana-Champaign. His interests lie in computer architecture, processor microarchitecture, energy-efficient system and processor architecture, and processing-in-memory.

Parallel systems has been a central part of the department's research focus since its founding in 1974. Early work on the Rochester Intelligent Gateway (RIG) project was the direct predecessor to the Accent and Mach projects at CMU, led by UR alum Rick Rashid (now senior vice president for research at Microsoft). These in turn led to such commercially important operating systems as Compaq Tru64 and Apple MacOS X.

In the mid to late 1980s, the department's 128-node Butterfly Parallel Processor was the largest parallel computer anywhere in academia. It supported a wide variety of projects, including the Instant Replay debugging system, the Bridge parallel file system, the Elmwood and Psyche parallel operating systems, and the development of contention-free synchronization. Our work from this era is very heavily cited, and has influenced the research of many other groups.

Today our research spans a wide range of topics, including:

  • Program analysis and compiler technology
  • Parallel, distributed, and mobile computing
  • Cluster and cloud computing
  • Low-power hardware and software
  • Processor and memory architecture
  • Operating systems and security
  • Concurrency and synchronization

One of the strengths of the group is the way in which each faculty member's research interests tie into the others', allowing us to leverage infrastructure developed by the group as a whole. We therefore interact closely with the parallel user community, including researchers in astrophysics, data science, chemistry, biology, laser energetics, and, within our own department, computer vision, robotics, and machine learning. The multi-PI Computer Systems and Engineering Group spans the CS and ECE departments.

Professor Dwarkadas's work on the TreadMarks and FASTLINK projects, in collaboration with colleagues at Rice University and at the National Institutes of Health, was instrumental in discovering the gene believed responsible for Parkinson's disease. The work of former professor Kai Shen (now at Google) on cluster management was the technology behind Several algorithms from Professor Scott's group appear in the Java standard library.

The systems group enjoys outstanding computational resources. Current research infrastructure includes a large Linux cluster, a 72-thread (36-core) Intel Haswell machine, an 80-thread (40-core) Intel Skylake machine, an 160-thread (20-core) IBM Power8 server, and a variety of smaller x86 machines. The group also also enjoys access to a variety of machines at the University's Center for Integrated Research Computing, the Laboratory for Laser Energetics, the IBM Canada Centres for Advanced Studies, and other sites.

Project Pages

Project NameBrief Summary
BOP: Behavior-oriented Parallelization aka Parallel Programming by Hints

Behavior-oriented parallelization (BOP) provides a suggestion interface for a user to mark possible parallelism and run-time support to guarante correctness and efficient execution whether the hints are correct or not.  It enables program parallelization based on partial information and is useful for incrementally parallelizing a program or streamlining it for common uses.

Compiler Research, including Distance- and Footprint-Based Locality Analysis and Optimization

Our compiler research addresses the twin concerns of correctness and performance, with a focus on recurrence in the use of data—determining whether a complex program has an inherent pattern of data reuse and, if so, to what degree that pattern can be modeled, measured, and modified (improved).

CoSyn: Communication and Synchronization Mechanisms for Emerging Multi-Core Processors

This project addresses the challenge of mainstream parallelism using a combined hardware-software approach. The key idea is to identify common time-critical operations, across a variety of applications and programming models, that might be accelerated or simplified by new architectural mechanisms, and then to design those mechanisms in as general a fashion as possible. Candidate mechanisms include the alert-on-update notification mechanism, programmable data isolation, adaptive cooperative caching, and fine-grain access control.

High-Performance Synchronization for Shared-Memory Parallel Programs

Synchronization serves to constrain the interleaving of actions performed by multiple threads of control (e.g., on a multicore processor), allowing only correct executions.  Over the years, this ongoing project has developed some of the most efficient and widely used algorithms for locking, concurrent data structures, transactional memory, and persistence.

Performance Modeling and Anomaly Management for Complex Systems

This project investigates profile-driven performance models for multi-component, data-intensive online service.  It explores a variety of techniques, and has, among other things, identified previously unknown I/O performance bugs in Linux.

Reuse Distance and Footprint Based Locality Analysis and Optimization

Reuse distance and program footprint are two basic metrics we use to study the twin concerns of memory system performance and correctness, with a focus on recurrence in the use of data—determining whether a complex program has an inherent pattern of data reuse and, if so, to what degree that pattern can be modeled, measured, and modified (improved).

Rochester Memory Hardware Error Research Project

This project monitors computers in the field, in real time, and records memory errors as they occur. It reveals that soft (transient) errors are orders of magnitude less frequent than previously reported.  It combines the soft and hard (permanent) error rates to predict failure rates and patterns for systems as a whole.

The Rochester Software Transactional Memory (RSTM) system

Transactional memory (TM) allows programmers to specify operations that should execute atomically, without worrying about how that atomicity should be achieved.  Downloaded to thousands of sites worldwide, RSTM provides a diverse suite of efficient, mutually compatible TM run-time systems.

System Support for Fast Computational Accelerators

Programmable GPUs are now central to power-efficient computing across the full spectrum from cell phones to supercomputers.  We are developing techniques to share access to these and future accelerators among mutually untrusting applications, despite highly variable execution times, bandwidth requirements that stretch the capabilities of hosting CPUs, and communication channels that may bypass the operating system.